/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_BPS_H
#define TITAN170_BPS_H

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define BPS_REGS_FIRST 0x0 

#define BPS_REGS_LAST 0x72fc 

#define BPS_REGS_COUNT 0x444 

#define regBPS_BPS_0_CDM_HW_VERSION 0x0  /*register offset*/
#define BPS_BPS_0_CDM_HW_VERSION_REVISION_MASK 0xffff
#define BPS_BPS_0_CDM_HW_VERSION_REVISION_SHIFT 0x0
#define BPS_BPS_0_CDM_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
#define BPS_BPS_0_CDM_HW_VERSION_MINOR_VERSION_SHIFT 0x10
#define BPS_BPS_0_CDM_HW_VERSION_MAJOR_VERSION_MASK 0xf0000000
#define BPS_BPS_0_CDM_HW_VERSION_MAJOR_VERSION_SHIFT 0x1c

#define regBPS_BPS_0_CDM_TITAN_VERSION 0x4  /*register offset*/
#define BPS_BPS_0_CDM_TITAN_VERSION_STEP_MASK 0xff
#define BPS_BPS_0_CDM_TITAN_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CDM_TITAN_VERSION_TIER_MASK 0xff00
#define BPS_BPS_0_CDM_TITAN_VERSION_TIER_SHIFT 0x8
#define BPS_BPS_0_CDM_TITAN_VERSION_GENERATION_MASK 0xff0000
#define BPS_BPS_0_CDM_TITAN_VERSION_GENERATION_SHIFT 0x10
#define BPS_BPS_0_CDM_TITAN_VERSION_UNUSED0_MASK 0xff000000
#define BPS_BPS_0_CDM_TITAN_VERSION_UNUSED0_SHIFT 0x18

#define regBPS_BPS_0_CDM_RST_CMD 0x10  /*register offset*/
#define BPS_BPS_0_CDM_RST_CMD_CORE_RST_STB_MASK 0x1
#define BPS_BPS_0_CDM_RST_CMD_CORE_RST_STB_SHIFT 0x0
#define BPS_BPS_0_CDM_RST_CMD_PERF_MON_RST_STB_MASK 0x2
#define BPS_BPS_0_CDM_RST_CMD_PERF_MON_RST_STB_SHIFT 0x1
#define BPS_BPS_0_CDM_RST_CMD_MISR_RST_STB_MASK 0x4
#define BPS_BPS_0_CDM_RST_CMD_MISR_RST_STB_SHIFT 0x2
#define BPS_BPS_0_CDM_RST_CMD_BL_FIFO_RST_STB_MASK 0x8
#define BPS_BPS_0_CDM_RST_CMD_BL_FIFO_RST_STB_SHIFT 0x3
#define BPS_BPS_0_CDM_RST_CMD_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_CDM_RST_CMD_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_CDM_CGC_CFG 0x14  /*register offset*/
#define BPS_BPS_0_CDM_CGC_CFG_CDM_CGC_OVERRIDE_MASK 0x1
#define BPS_BPS_0_CDM_CGC_CFG_CDM_CGC_OVERRIDE_SHIFT 0x0
#define BPS_BPS_0_CDM_CGC_CFG_AHB_CGC_OVERRIDE_MASK 0x2
#define BPS_BPS_0_CDM_CGC_CFG_AHB_CGC_OVERRIDE_SHIFT 0x1
#define BPS_BPS_0_CDM_CGC_CFG_RIF_CGC_OVERRIDE_MASK 0x4
#define BPS_BPS_0_CDM_CGC_CFG_RIF_CGC_OVERRIDE_SHIFT 0x2
#define BPS_BPS_0_CDM_CGC_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CDM_CGC_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CDM_CORE_CFG 0x18  /*register offset*/
#define BPS_BPS_0_CDM_CORE_CFG_AHB_BURST_LEN_MASK 0xf
#define BPS_BPS_0_CDM_CORE_CFG_AHB_BURST_LEN_SHIFT 0x0
#define BPS_BPS_0_CDM_CORE_CFG_AHB_BURST_EN_MASK 0x10
#define BPS_BPS_0_CDM_CORE_CFG_AHB_BURST_EN_SHIFT 0x4
#define BPS_BPS_0_CDM_CORE_CFG_UNUSED0_MASK 0xe0
#define BPS_BPS_0_CDM_CORE_CFG_UNUSED0_SHIFT 0x5
#define BPS_BPS_0_CDM_CORE_CFG_AHB_STOP_ON_ERROR_MASK 0x100
#define BPS_BPS_0_CDM_CORE_CFG_AHB_STOP_ON_ERROR_SHIFT 0x8
#define BPS_BPS_0_CDM_CORE_CFG_UNUSED1_MASK 0xfffffe00
#define BPS_BPS_0_CDM_CORE_CFG_UNUSED1_SHIFT 0x9

#define regBPS_BPS_0_CDM_CORE_EN 0x1c  /*register offset*/
#define BPS_BPS_0_CDM_CORE_EN_CDM_EN_MASK 0x1
#define BPS_BPS_0_CDM_CORE_EN_CDM_EN_SHIFT 0x0
#define BPS_BPS_0_CDM_CORE_EN_CDM_PAUSE_MASK 0x2
#define BPS_BPS_0_CDM_CORE_EN_CDM_PAUSE_SHIFT 0x1
#define BPS_BPS_0_CDM_CORE_EN_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CDM_CORE_EN_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CDM_FE_CFG 0x20  /*register offset*/
#define BPS_BPS_0_CDM_FE_CFG_AXI_BURST_LEN_MASK 0xf
#define BPS_BPS_0_CDM_FE_CFG_AXI_BURST_LEN_SHIFT 0x0
#define BPS_BPS_0_CDM_FE_CFG_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CDM_FE_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CDM_FE_CFG_BUS_RD_CLIENT_REQ_DATA_CNTR_MAX_MASK 0xffff0000
#define BPS_BPS_0_CDM_FE_CFG_BUS_RD_CLIENT_REQ_DATA_CNTR_MAX_SHIFT 0x10

#define regBPS_BPS_0_CDM_IRQ_MASK 0x30  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_MASK_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_CDM_IRQ_MASK_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_CDM_IRQ_MASK_INFO_INLINE_IRQ_MASK 0x2
#define BPS_BPS_0_CDM_IRQ_MASK_INFO_INLINE_IRQ_SHIFT 0x1
#define BPS_BPS_0_CDM_IRQ_MASK_INFO_BL_DONE_MASK 0x4
#define BPS_BPS_0_CDM_IRQ_MASK_INFO_BL_DONE_SHIFT 0x2
#define BPS_BPS_0_CDM_IRQ_MASK_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_CDM_IRQ_MASK_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CDM_IRQ_MASK_ERROR_INV_CMD_MASK 0x10000
#define BPS_BPS_0_CDM_IRQ_MASK_ERROR_INV_CMD_SHIFT 0x10
#define BPS_BPS_0_CDM_IRQ_MASK_ERROR_OVER_FLOW_MASK 0x20000
#define BPS_BPS_0_CDM_IRQ_MASK_ERROR_OVER_FLOW_SHIFT 0x11
#define BPS_BPS_0_CDM_IRQ_MASK_ERROR_AHB_BUS_MASK 0x40000
#define BPS_BPS_0_CDM_IRQ_MASK_ERROR_AHB_BUS_SHIFT 0x12
#define BPS_BPS_0_CDM_IRQ_MASK_UNUSED1_MASK 0xfff80000
#define BPS_BPS_0_CDM_IRQ_MASK_UNUSED1_SHIFT 0x13

#define regBPS_BPS_0_CDM_IRQ_CLEAR 0x34  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_CLEAR_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_CDM_IRQ_CLEAR_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_CDM_IRQ_CLEAR_INFO_INLINE_IRQ_MASK 0x2
#define BPS_BPS_0_CDM_IRQ_CLEAR_INFO_INLINE_IRQ_SHIFT 0x1
#define BPS_BPS_0_CDM_IRQ_CLEAR_INFO_BL_DONE_MASK 0x4
#define BPS_BPS_0_CDM_IRQ_CLEAR_INFO_BL_DONE_SHIFT 0x2
#define BPS_BPS_0_CDM_IRQ_CLEAR_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_CDM_IRQ_CLEAR_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CDM_IRQ_CLEAR_ERROR_INV_CMD_MASK 0x10000
#define BPS_BPS_0_CDM_IRQ_CLEAR_ERROR_INV_CMD_SHIFT 0x10
#define BPS_BPS_0_CDM_IRQ_CLEAR_ERROR_OVER_FLOW_MASK 0x20000
#define BPS_BPS_0_CDM_IRQ_CLEAR_ERROR_OVER_FLOW_SHIFT 0x11
#define BPS_BPS_0_CDM_IRQ_CLEAR_ERROR_AHB_BUS_MASK 0x40000
#define BPS_BPS_0_CDM_IRQ_CLEAR_ERROR_AHB_BUS_SHIFT 0x12
#define BPS_BPS_0_CDM_IRQ_CLEAR_UNUSED1_MASK 0xfff80000
#define BPS_BPS_0_CDM_IRQ_CLEAR_UNUSED1_SHIFT 0x13

#define regBPS_BPS_0_CDM_IRQ_CLEAR_CMD 0x38  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_CLEAR_CMD_IRQ_CLEAR_CMD_MASK 0x1
#define BPS_BPS_0_CDM_IRQ_CLEAR_CMD_IRQ_CLEAR_CMD_SHIFT 0x0
#define BPS_BPS_0_CDM_IRQ_CLEAR_CMD_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CDM_IRQ_CLEAR_CMD_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CDM_IRQ_SET 0x3c  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_SET_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_CDM_IRQ_SET_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_CDM_IRQ_SET_INFO_INLINE_IRQ_MASK 0x2
#define BPS_BPS_0_CDM_IRQ_SET_INFO_INLINE_IRQ_SHIFT 0x1
#define BPS_BPS_0_CDM_IRQ_SET_INFO_BL_DONE_MASK 0x4
#define BPS_BPS_0_CDM_IRQ_SET_INFO_BL_DONE_SHIFT 0x2
#define BPS_BPS_0_CDM_IRQ_SET_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_CDM_IRQ_SET_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CDM_IRQ_SET_ERROR_INV_CMD_MASK 0x10000
#define BPS_BPS_0_CDM_IRQ_SET_ERROR_INV_CMD_SHIFT 0x10
#define BPS_BPS_0_CDM_IRQ_SET_ERROR_OVER_FLOW_MASK 0x20000
#define BPS_BPS_0_CDM_IRQ_SET_ERROR_OVER_FLOW_SHIFT 0x11
#define BPS_BPS_0_CDM_IRQ_SET_ERROR_AHB_BUS_MASK 0x40000
#define BPS_BPS_0_CDM_IRQ_SET_ERROR_AHB_BUS_SHIFT 0x12
#define BPS_BPS_0_CDM_IRQ_SET_UNUSED1_MASK 0xfff80000
#define BPS_BPS_0_CDM_IRQ_SET_UNUSED1_SHIFT 0x13

#define regBPS_BPS_0_CDM_IRQ_SET_CMD 0x40  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_SET_CMD_IRQ_SET_CMD_MASK 0x1
#define BPS_BPS_0_CDM_IRQ_SET_CMD_IRQ_SET_CMD_SHIFT 0x0
#define BPS_BPS_0_CDM_IRQ_SET_CMD_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CDM_IRQ_SET_CMD_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CDM_IRQ_STATUS 0x44  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_STATUS_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_CDM_IRQ_STATUS_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_CDM_IRQ_STATUS_INFO_INLINE_IRQ_MASK 0x2
#define BPS_BPS_0_CDM_IRQ_STATUS_INFO_INLINE_IRQ_SHIFT 0x1
#define BPS_BPS_0_CDM_IRQ_STATUS_INFO_BL_DONE_MASK 0x4
#define BPS_BPS_0_CDM_IRQ_STATUS_INFO_BL_DONE_SHIFT 0x2
#define BPS_BPS_0_CDM_IRQ_STATUS_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_CDM_IRQ_STATUS_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000
#define BPS_BPS_0_CDM_IRQ_STATUS_ERROR_INV_CMD_SHIFT 0x10
#define BPS_BPS_0_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000
#define BPS_BPS_0_CDM_IRQ_STATUS_ERROR_OVER_FLOW_SHIFT 0x11
#define BPS_BPS_0_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000
#define BPS_BPS_0_CDM_IRQ_STATUS_ERROR_AHB_BUS_SHIFT 0x12
#define BPS_BPS_0_CDM_IRQ_STATUS_UNUSED1_MASK 0xfff80000
#define BPS_BPS_0_CDM_IRQ_STATUS_UNUSED1_SHIFT 0x13

#define regBPS_BPS_0_CDM_BL_FIFO_BASE_REG 0x50  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_BASE_REG_BASE_MASK 0xffffffff
#define BPS_BPS_0_CDM_BL_FIFO_BASE_REG_BASE_SHIFT 0x0

#define regBPS_BPS_0_CDM_BL_FIFO_LEN_REG 0x54  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_LEN_REG_LEN_MASK 0xfffff
#define BPS_BPS_0_CDM_BL_FIFO_LEN_REG_LEN_SHIFT 0x0
#define BPS_BPS_0_CDM_BL_FIFO_LEN_REG_UNUSED0_MASK 0xf00000
#define BPS_BPS_0_CDM_BL_FIFO_LEN_REG_UNUSED0_SHIFT 0x14
#define BPS_BPS_0_CDM_BL_FIFO_LEN_REG_TAG_MASK 0xff000000
#define BPS_BPS_0_CDM_BL_FIFO_LEN_REG_TAG_SHIFT 0x18

#define regBPS_BPS_0_CDM_BL_FIFO_STORE_REG 0x58  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_STORE_REG_COMMIT_MASK 0x1
#define BPS_BPS_0_CDM_BL_FIFO_STORE_REG_COMMIT_SHIFT 0x0
#define BPS_BPS_0_CDM_BL_FIFO_STORE_REG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CDM_BL_FIFO_STORE_REG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CDM_BL_FIFO_CFG 0x5c  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_MASK 0x3
#define BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_SHIFT 0x0
#define BPS_BPS_0_CDM_BL_FIFO_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CDM_BL_FIFO_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CDM_BL_FIFO_RB 0x60  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_RB_FIFO_OFFSET_MASK 0x3f
#define BPS_BPS_0_CDM_BL_FIFO_RB_FIFO_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CDM_BL_FIFO_RB_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CDM_BL_FIFO_RB_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CDM_BL_FIFO_BASE_RB 0x64  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_BASE_RB_BASE_MASK 0xffffffff
#define BPS_BPS_0_CDM_BL_FIFO_BASE_RB_BASE_SHIFT 0x0

#define regBPS_BPS_0_CDM_BL_FIFO_LEN_RB 0x68  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_LEN_RB_LEN_MASK 0xfffff
#define BPS_BPS_0_CDM_BL_FIFO_LEN_RB_LEN_SHIFT 0x0
#define BPS_BPS_0_CDM_BL_FIFO_LEN_RB_UNUSED0_MASK 0xf00000
#define BPS_BPS_0_CDM_BL_FIFO_LEN_RB_UNUSED0_SHIFT 0x14
#define BPS_BPS_0_CDM_BL_FIFO_LEN_RB_TAG_MASK 0xff000000
#define BPS_BPS_0_CDM_BL_FIFO_LEN_RB_TAG_SHIFT 0x18

#define regBPS_BPS_0_CDM_BL_FIFO_PENDING_REQ_RB 0x6c  /*register offset*/
#define BPS_BPS_0_CDM_BL_FIFO_PENDING_REQ_RB_PENDING_REQ_MASK 0x7f
#define BPS_BPS_0_CDM_BL_FIFO_PENDING_REQ_RB_PENDING_REQ_SHIFT 0x0
#define BPS_BPS_0_CDM_BL_FIFO_PENDING_REQ_RB_UNUSED0_MASK 0xffffff80
#define BPS_BPS_0_CDM_BL_FIFO_PENDING_REQ_RB_UNUSED0_SHIFT 0x7

#define regBPS_BPS_0_CDM_IRQ_USR_DATA 0x80  /*register offset*/
#define BPS_BPS_0_CDM_IRQ_USR_DATA_VALUE_MASK 0xffffffff
#define BPS_BPS_0_CDM_IRQ_USR_DATA_VALUE_SHIFT 0x0

#define regBPS_BPS_0_CDM_WAIT_STATUS 0x84  /*register offset*/
#define BPS_BPS_0_CDM_WAIT_STATUS_MASK_MASK 0xff
#define BPS_BPS_0_CDM_WAIT_STATUS_MASK_SHIFT 0x0
#define BPS_BPS_0_CDM_WAIT_STATUS_ID_MASK 0xff00
#define BPS_BPS_0_CDM_WAIT_STATUS_ID_SHIFT 0x8
#define BPS_BPS_0_CDM_WAIT_STATUS_WAITING_MASK 0x10000
#define BPS_BPS_0_CDM_WAIT_STATUS_WAITING_SHIFT 0x10
#define BPS_BPS_0_CDM_WAIT_STATUS_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CDM_WAIT_STATUS_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CDM_COMP_WAIT_STATUS0 0x88  /*register offset*/
#define BPS_BPS_0_CDM_COMP_WAIT_STATUS0_WAITING_MASK 0xffffffff
#define BPS_BPS_0_CDM_COMP_WAIT_STATUS0_WAITING_SHIFT 0x0

#define regBPS_BPS_0_CDM_COMP_WAIT_STATUS1 0x8c  /*register offset*/
#define BPS_BPS_0_CDM_COMP_WAIT_STATUS1_WAITING_MASK 0xffffffff
#define BPS_BPS_0_CDM_COMP_WAIT_STATUS1_WAITING_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_0_REG 0x90  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_0_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_0_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_1_REG 0x94  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_1_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_1_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_2_REG 0x98  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_2_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_2_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_3_REG 0x9c  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_3_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_3_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_4_REG 0xa0  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_4_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_4_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_5_REG 0xa4  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_5_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_5_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_6_REG 0xa8  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_6_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_6_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_SCRATCH_7_REG 0xac  /*register offset*/
#define BPS_BPS_0_CDM_SCRATCH_7_REG_GP_REG_MASK 0xffffffff
#define BPS_BPS_0_CDM_SCRATCH_7_REG_GP_REG_SHIFT 0x0

#define regBPS_BPS_0_CDM_LAST_AHB_ADDR 0xd0  /*register offset*/
#define BPS_BPS_0_CDM_LAST_AHB_ADDR_ADDR_MASK 0xffffffff
#define BPS_BPS_0_CDM_LAST_AHB_ADDR_ADDR_SHIFT 0x0

#define regBPS_BPS_0_CDM_LAST_AHB_DATA 0xd4  /*register offset*/
#define BPS_BPS_0_CDM_LAST_AHB_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CDM_LAST_AHB_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CDM_CORE_DBUG 0xd8  /*register offset*/
#define BPS_BPS_0_CDM_CORE_DBUG_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CDM_CORE_DBUG_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CDM_CORE_DBUG_UNUSED0_MASK 0xe
#define BPS_BPS_0_CDM_CORE_DBUG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CDM_CORE_DBUG_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CDM_CORE_DBUG_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CDM_CORE_DBUG_LOG_AHB_MASK 0x100
#define BPS_BPS_0_CDM_CORE_DBUG_LOG_AHB_SHIFT 0x8
#define BPS_BPS_0_CDM_CORE_DBUG_UNUSED1_MASK 0xfe00
#define BPS_BPS_0_CDM_CORE_DBUG_UNUSED1_SHIFT 0x9
#define BPS_BPS_0_CDM_CORE_DBUG_BL_FIFO_RD_EN_MASK 0x10000
#define BPS_BPS_0_CDM_CORE_DBUG_BL_FIFO_RD_EN_SHIFT 0x10
#define BPS_BPS_0_CDM_CORE_DBUG_UNUSED2_MASK 0xfffe0000
#define BPS_BPS_0_CDM_CORE_DBUG_UNUSED2_SHIFT 0x11

#define regBPS_BPS_0_CDM_LAST_AHB_ERR_ADDR 0xe0  /*register offset*/
#define BPS_BPS_0_CDM_LAST_AHB_ERR_ADDR_ADDR_MASK 0xffffffff
#define BPS_BPS_0_CDM_LAST_AHB_ERR_ADDR_ADDR_SHIFT 0x0

#define regBPS_BPS_0_CDM_LAST_AHB_ERR_DATA 0xe4  /*register offset*/
#define BPS_BPS_0_CDM_LAST_AHB_ERR_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CDM_LAST_AHB_ERR_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CDM_CURRENT_BL_BASE 0xe8  /*register offset*/
#define BPS_BPS_0_CDM_CURRENT_BL_BASE_BASE_MASK 0xffffffff
#define BPS_BPS_0_CDM_CURRENT_BL_BASE_BASE_SHIFT 0x0

#define regBPS_BPS_0_CDM_CURRENT_BL_LEN 0xec  /*register offset*/
#define BPS_BPS_0_CDM_CURRENT_BL_LEN_LEN_MASK 0xfffff
#define BPS_BPS_0_CDM_CURRENT_BL_LEN_LEN_SHIFT 0x0
#define BPS_BPS_0_CDM_CURRENT_BL_LEN_UNUSED0_MASK 0xf00000
#define BPS_BPS_0_CDM_CURRENT_BL_LEN_UNUSED0_SHIFT 0x14
#define BPS_BPS_0_CDM_CURRENT_BL_LEN_TAG_MASK 0xff000000
#define BPS_BPS_0_CDM_CURRENT_BL_LEN_TAG_SHIFT 0x18

#define regBPS_BPS_0_CDM_CURRENT_USED_AHB_BASE 0xf0  /*register offset*/
#define BPS_BPS_0_CDM_CURRENT_USED_AHB_BASE_VALUE_MASK 0xffffff
#define BPS_BPS_0_CDM_CURRENT_USED_AHB_BASE_VALUE_SHIFT 0x0
#define BPS_BPS_0_CDM_CURRENT_USED_AHB_BASE_UNUSED0_MASK 0xff000000
#define BPS_BPS_0_CDM_CURRENT_USED_AHB_BASE_UNUSED0_SHIFT 0x18

#define regBPS_BPS_0_CDM_DEBUG_STATUS 0xf4  /*register offset*/
#define BPS_BPS_0_CDM_DEBUG_STATUS_VALUE_MASK 0xffffffff
#define BPS_BPS_0_CDM_DEBUG_STATUS_VALUE_SHIFT 0x0

#define regBPS_BPS_0_CDM_BUS_MISR_CFG_0 0x100  /*register offset*/
#define BPS_BPS_0_CDM_BUS_MISR_CFG_0_FE_SAMP_MODE_MASK 0x3
#define BPS_BPS_0_CDM_BUS_MISR_CFG_0_FE_SAMP_MODE_SHIFT 0x0
#define BPS_BPS_0_CDM_BUS_MISR_CFG_0_FE_ENABLE_MASK 0x4
#define BPS_BPS_0_CDM_BUS_MISR_CFG_0_FE_ENABLE_SHIFT 0x2
#define BPS_BPS_0_CDM_BUS_MISR_CFG_0_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CDM_BUS_MISR_CFG_0_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CDM_BUS_MISR_CFG_1 0x104  /*register offset*/
#define BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_MASK 0x3
#define BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_CDM_BUS_MISR_CFG_1_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CDM_BUS_MISR_CFG_1_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CDM_BUS_MISR_RD_VAL 0x108  /*register offset*/
#define BPS_BPS_0_CDM_BUS_MISR_RD_VAL_MISR_VAL_MASK 0xffffffff
#define BPS_BPS_0_CDM_BUS_MISR_RD_VAL_MISR_VAL_SHIFT 0x0

#define regBPS_BPS_0_CDM_PERF_MON_CTRL 0x110  /*register offset*/
#define BPS_BPS_0_CDM_PERF_MON_CTRL_PERF_MON_EN_MASK 0x1
#define BPS_BPS_0_CDM_PERF_MON_CTRL_PERF_MON_EN_SHIFT 0x0
#define BPS_BPS_0_CDM_PERF_MON_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CDM_PERF_MON_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CDM_PERF_MON_0 0x114  /*register offset*/
#define BPS_BPS_0_CDM_PERF_MON_0_TOTAL_CYCLES_MASK 0xffffffff
#define BPS_BPS_0_CDM_PERF_MON_0_TOTAL_CYCLES_SHIFT 0x0

#define regBPS_BPS_0_CDM_PERF_MON_1 0x118  /*register offset*/
#define BPS_BPS_0_CDM_PERF_MON_1_TOTAL_CYCLES_MASK 0xffffffff
#define BPS_BPS_0_CDM_PERF_MON_1_TOTAL_CYCLES_SHIFT 0x0

#define regBPS_BPS_0_CDM_PERF_MON_2 0x11c  /*register offset*/
#define BPS_BPS_0_CDM_PERF_MON_2_TOTAL_CYCLES_MASK 0xffffffff
#define BPS_BPS_0_CDM_PERF_MON_2_TOTAL_CYCLES_SHIFT 0x0

#define regBPS_BPS_0_CDM_SPARE 0x1fc  /*register offset*/
#define BPS_BPS_0_CDM_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CDM_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CDM_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CDM_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_HW_VERSION 0x1000  /*register offset*/
#define BPS_BPS_0_HW_VERSION_REVISION_MASK 0xffff
#define BPS_BPS_0_HW_VERSION_REVISION_SHIFT 0x0
#define BPS_BPS_0_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
#define BPS_BPS_0_HW_VERSION_MINOR_VERSION_SHIFT 0x10
#define BPS_BPS_0_HW_VERSION_MAJOR_VERSION_MASK 0xf0000000
#define BPS_BPS_0_HW_VERSION_MAJOR_VERSION_SHIFT 0x1c

#define regBPS_BPS_0_TITAN_VERSION 0x1004  /*register offset*/
#define BPS_BPS_0_TITAN_VERSION_STEP_MASK 0xff
#define BPS_BPS_0_TITAN_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_TITAN_VERSION_TIER_MASK 0xff00
#define BPS_BPS_0_TITAN_VERSION_TIER_SHIFT 0x8
#define BPS_BPS_0_TITAN_VERSION_GENERATION_MASK 0xff0000
#define BPS_BPS_0_TITAN_VERSION_GENERATION_SHIFT 0x10
#define BPS_BPS_0_TITAN_VERSION_UNUSED0_MASK 0xff000000
#define BPS_BPS_0_TITAN_VERSION_UNUSED0_SHIFT 0x18

#define regBPS_BPS_0_RST_CMD 0x1008  /*register offset*/
#define BPS_BPS_0_RST_CMD_HW_MOD_RST_MASK 0x1
#define BPS_BPS_0_RST_CMD_HW_MOD_RST_SHIFT 0x0
#define BPS_BPS_0_RST_CMD_SW_REG_RST_MASK 0x2
#define BPS_BPS_0_RST_CMD_SW_REG_RST_SHIFT 0x1
#define BPS_BPS_0_RST_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_RST_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_IRQ_STATUS 0x100c  /*register offset*/
#define BPS_BPS_0_IRQ_STATUS_RST_DONE_IRQ_MASK 0x1
#define BPS_BPS_0_IRQ_STATUS_RST_DONE_IRQ_SHIFT 0x0
#define BPS_BPS_0_IRQ_STATUS_WE_IRQ_MASK 0x2
#define BPS_BPS_0_IRQ_STATUS_WE_IRQ_SHIFT 0x1
#define BPS_BPS_0_IRQ_STATUS_FE_IRQ_MASK 0x4
#define BPS_BPS_0_IRQ_STATUS_FE_IRQ_SHIFT 0x2
#define BPS_BPS_0_IRQ_STATUS_BPS_IRQ_MASK 0x8
#define BPS_BPS_0_IRQ_STATUS_BPS_IRQ_SHIFT 0x3
#define BPS_BPS_0_IRQ_STATUS_IDLE_IRQ_MASK 0x10
#define BPS_BPS_0_IRQ_STATUS_IDLE_IRQ_SHIFT 0x4
#define BPS_BPS_0_IRQ_STATUS_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_IRQ_STATUS_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_IRQ_MASK 0x1010  /*register offset*/
#define BPS_BPS_0_IRQ_MASK_RST_DONE_IRQ_MASK_MASK 0x1
#define BPS_BPS_0_IRQ_MASK_RST_DONE_IRQ_MASK_SHIFT 0x0
#define BPS_BPS_0_IRQ_MASK_WE_IRQ_MASK_MASK 0x2
#define BPS_BPS_0_IRQ_MASK_WE_IRQ_MASK_SHIFT 0x1
#define BPS_BPS_0_IRQ_MASK_FE_IRQ_MASK_MASK 0x4
#define BPS_BPS_0_IRQ_MASK_FE_IRQ_MASK_SHIFT 0x2
#define BPS_BPS_0_IRQ_MASK_BPS_IRQ_MASK_MASK 0x8
#define BPS_BPS_0_IRQ_MASK_BPS_IRQ_MASK_SHIFT 0x3
#define BPS_BPS_0_IRQ_MASK_IDLE_IRQ_MASK_MASK 0x10
#define BPS_BPS_0_IRQ_MASK_IDLE_IRQ_MASK_SHIFT 0x4
#define BPS_BPS_0_IRQ_MASK_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_IRQ_MASK_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_IRQ_CLEAR 0x1014  /*register offset*/
#define BPS_BPS_0_IRQ_CLEAR_RST_DONE_IRQ_CLEAR_MASK 0x1
#define BPS_BPS_0_IRQ_CLEAR_RST_DONE_IRQ_CLEAR_SHIFT 0x0
#define BPS_BPS_0_IRQ_CLEAR_WE_IRQ_CLEAR_MASK 0x2
#define BPS_BPS_0_IRQ_CLEAR_WE_IRQ_CLEAR_SHIFT 0x1
#define BPS_BPS_0_IRQ_CLEAR_FE_IRQ_CLEAR_MASK 0x4
#define BPS_BPS_0_IRQ_CLEAR_FE_IRQ_CLEAR_SHIFT 0x2
#define BPS_BPS_0_IRQ_CLEAR_BPS_IRQ_CLEAR_MASK 0x8
#define BPS_BPS_0_IRQ_CLEAR_BPS_IRQ_CLEAR_SHIFT 0x3
#define BPS_BPS_0_IRQ_CLEAR_IDLE_IRQ_CLEAR_MASK 0x10
#define BPS_BPS_0_IRQ_CLEAR_IDLE_IRQ_CLEAR_SHIFT 0x4
#define BPS_BPS_0_IRQ_CLEAR_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_IRQ_CLEAR_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_IRQ_SET 0x1018  /*register offset*/
#define BPS_BPS_0_IRQ_SET_RST_DONE_IRQ_SET_MASK 0x1
#define BPS_BPS_0_IRQ_SET_RST_DONE_IRQ_SET_SHIFT 0x0
#define BPS_BPS_0_IRQ_SET_WE_IRQ_SET_MASK 0x2
#define BPS_BPS_0_IRQ_SET_WE_IRQ_SET_SHIFT 0x1
#define BPS_BPS_0_IRQ_SET_FE_IRQ_SET_MASK 0x4
#define BPS_BPS_0_IRQ_SET_FE_IRQ_SET_SHIFT 0x2
#define BPS_BPS_0_IRQ_SET_BPS_IRQ_SET_MASK 0x8
#define BPS_BPS_0_IRQ_SET_BPS_IRQ_SET_SHIFT 0x3
#define BPS_BPS_0_IRQ_SET_IDLE_IRQ_SET_MASK 0x10
#define BPS_BPS_0_IRQ_SET_IDLE_IRQ_SET_SHIFT 0x4
#define BPS_BPS_0_IRQ_SET_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_IRQ_SET_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_IRQ_CMD 0x101c  /*register offset*/
#define BPS_BPS_0_IRQ_CMD_CLEAR_MASK 0x1
#define BPS_BPS_0_IRQ_CMD_CLEAR_SHIFT 0x0
#define BPS_BPS_0_IRQ_CMD_UNUSED0_MASK 0xe
#define BPS_BPS_0_IRQ_CMD_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_IRQ_CMD_SET_MASK 0x10
#define BPS_BPS_0_IRQ_CMD_SET_SHIFT 0x4
#define BPS_BPS_0_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define BPS_BPS_0_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regBPS_BPS_0_CORE_CLK_CFG_0 0x1020  /*register offset*/
#define BPS_BPS_0_CORE_CLK_CFG_0_BPS_CORE_CLK_CGC_OVERRIDE_MASK 0x1
#define BPS_BPS_0_CORE_CLK_CFG_0_BPS_CORE_CLK_CGC_OVERRIDE_SHIFT 0x0
#define BPS_BPS_0_CORE_CLK_CFG_0_FE_CORE_CLK_CGC_OVERRIDE_MASK 0x2
#define BPS_BPS_0_CORE_CLK_CFG_0_FE_CORE_CLK_CGC_OVERRIDE_SHIFT 0x1
#define BPS_BPS_0_CORE_CLK_CFG_0_WE_CORE_CLK_CGC_OVERRIDE_MASK 0x4
#define BPS_BPS_0_CORE_CLK_CFG_0_WE_CORE_CLK_CGC_OVERRIDE_SHIFT 0x2
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_PEDESTAL_CORE_CLK_CGC_OVERRIDE_MASK 0x8
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_PEDESTAL_CORE_CLK_CGC_OVERRIDE_SHIFT 0x3
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_LINEARIZATION_CORE_CLK_CGC_OVERRIDE_MASK 0x10
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_LINEARIZATION_CORE_CLK_CGC_OVERRIDE_SHIFT 0x4
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_BPC_PDPC_CORE_CLK_CGC_OVERRIDE_MASK 0x20
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_BPC_PDPC_CORE_CLK_CGC_OVERRIDE_SHIFT 0x5
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HDR_RECON_CORE_CLK_CGC_OVERRIDE_MASK 0x40
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HDR_RECON_CORE_CLK_CGC_OVERRIDE_SHIFT 0x6
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HDR_MAC_CORE_CLK_CGC_OVERRIDE_MASK 0x80
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HDR_MAC_CORE_CLK_CGC_OVERRIDE_SHIFT 0x7
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_GIC_CORE_CLK_CGC_OVERRIDE_MASK 0x100
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_GIC_CORE_CLK_CGC_OVERRIDE_SHIFT 0x8
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_ABF_CORE_CLK_CGC_OVERRIDE_MASK 0x200
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_ABF_CORE_CLK_CGC_OVERRIDE_SHIFT 0x9
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_LENS_ROLLOFF_CORE_CLK_CGC_OVERRIDE_MASK 0x400
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_LENS_ROLLOFF_CORE_CLK_CGC_OVERRIDE_SHIFT 0xa
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DEMO_CORE_CLK_CGC_OVERRIDE_MASK 0x800
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DEMO_CORE_CLK_CGC_OVERRIDE_SHIFT 0xb
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_BG_STATS_CORE_CLK_CGC_OVERRIDE_MASK 0x1000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_BG_STATS_CORE_CLK_CGC_OVERRIDE_SHIFT 0xc
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HDR_BHIST_STATS_CORE_CLK_CGC_OVERRIDE_MASK 0x2000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HDR_BHIST_STATS_CORE_CLK_CGC_OVERRIDE_SHIFT 0xd
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_COLOR_CORRECT_CORE_CLK_CGC_OVERRIDE_MASK 0x4000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_COLOR_CORRECT_CORE_CLK_CGC_OVERRIDE_SHIFT 0xe
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_GTM_CORE_CLK_CGC_OVERRIDE_MASK 0x8000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_GTM_CORE_CLK_CGC_OVERRIDE_SHIFT 0xf
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_GLUT_CORE_CLK_CGC_OVERRIDE_MASK 0x10000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_GLUT_CORE_CLK_CGC_OVERRIDE_SHIFT 0x10
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_COLOR_XFORM_CORE_CLK_CGC_OVERRIDE_MASK 0x20000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_COLOR_XFORM_CORE_CLK_CGC_OVERRIDE_SHIFT 0x11
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_MN_Y_CORE_CLK_CGC_OVERRIDE_MASK 0x40000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_MN_Y_CORE_CLK_CGC_OVERRIDE_SHIFT 0x12
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_MN_C_CORE_CLK_CGC_OVERRIDE_MASK 0x80000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_MN_C_CORE_CLK_CGC_OVERRIDE_SHIFT 0x13
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_4TO1_Y_CORE_CLK_CGC_OVERRIDE_MASK 0x100000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_4TO1_Y_CORE_CLK_CGC_OVERRIDE_SHIFT 0x14
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_4TO1_C_CORE_CLK_CGC_OVERRIDE_MASK 0x200000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DOWNSCALE_4TO1_C_CORE_CLK_CGC_OVERRIDE_SHIFT 0x15
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_R2PD_CORE_CLK_CGC_OVERRIDE_MASK 0x400000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_R2PD_CORE_CLK_CGC_OVERRIDE_SHIFT 0x16
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_CROP_RND_CLAMP_CORE_CLK_CGC_OVERRIDE_MASK 0x800000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_CROP_RND_CLAMP_CORE_CLK_CGC_OVERRIDE_SHIFT 0x17
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_PD2R_CORE_CLK_CGC_OVERRIDE_MASK 0x1000000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_PD2R_CORE_CLK_CGC_OVERRIDE_SHIFT 0x18
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DEMUX_CORE_CLK_CGC_OVERRIDE_MASK 0x2000000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_DEMUX_CORE_CLK_CGC_OVERRIDE_SHIFT 0x19
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HNR_CORE_CLK_CGC_OVERRIDE_MASK 0x4000000
#define BPS_BPS_0_CORE_CLK_CFG_0_CLC_HNR_CORE_CLK_CGC_OVERRIDE_SHIFT 0x1a
#define BPS_BPS_0_CORE_CLK_CFG_0_UNUSED0_MASK 0xf8000000
#define BPS_BPS_0_CORE_CLK_CFG_0_UNUSED0_SHIFT 0x1b

#define regBPS_BPS_0_CORE_CLK_CFG_1 0x1024  /*register offset*/
#define BPS_BPS_0_CORE_CLK_CFG_1_BPS_AHB_CLK_CGC_OVERRIDE_MASK 0x1
#define BPS_BPS_0_CORE_CLK_CFG_1_BPS_AHB_CLK_CGC_OVERRIDE_SHIFT 0x0
#define BPS_BPS_0_CORE_CLK_CFG_1_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CORE_CLK_CFG_1_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CORE_CLK_CFG_2 0x1028  /*register offset*/
#define BPS_BPS_0_CORE_CLK_CFG_2_BPS_NOC_CLK_CGC_OVERRIDE_MASK 0x1
#define BPS_BPS_0_CORE_CLK_CFG_2_BPS_NOC_CLK_CGC_OVERRIDE_SHIFT 0x0
#define BPS_BPS_0_CORE_CLK_CFG_2_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CORE_CLK_CFG_2_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CORE_CFG 0x102c  /*register offset*/
#define BPS_BPS_0_CORE_CFG_INPUT_FORMAT_MASK 0x3
#define BPS_BPS_0_CORE_CFG_INPUT_FORMAT_SHIFT 0x0
#define BPS_BPS_0_CORE_CFG_UNUSED0_MASK 0xc
#define BPS_BPS_0_CORE_CFG_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_CORE_CFG_OUTPUT_FORMAT_FULL_DS4_MASK 0x10
#define BPS_BPS_0_CORE_CFG_OUTPUT_FORMAT_FULL_DS4_SHIFT 0x4
#define BPS_BPS_0_CORE_CFG_UNUSED1_MASK 0xe0
#define BPS_BPS_0_CORE_CFG_UNUSED1_SHIFT 0x5
#define BPS_BPS_0_CORE_CFG_OUTPUT_FORMAT_PACK_BAYER_ARGB_MASK 0x700
#define BPS_BPS_0_CORE_CFG_OUTPUT_FORMAT_PACK_BAYER_ARGB_SHIFT 0x8
#define BPS_BPS_0_CORE_CFG_UNUSED2_MASK 0xf800
#define BPS_BPS_0_CORE_CFG_UNUSED2_SHIFT 0xb
#define BPS_BPS_0_CORE_CFG_ARGB_ALPHA_MASK 0xffff0000
#define BPS_BPS_0_CORE_CFG_ARGB_ALPHA_SHIFT 0x10

#define regBPS_BPS_0_VIOLATION_STATUS 0x1030  /*register offset*/
#define BPS_BPS_0_VIOLATION_STATUS_VIOLATION_STATUS_MASK 0x3f
#define BPS_BPS_0_VIOLATION_STATUS_VIOLATION_STATUS_SHIFT 0x0
#define BPS_BPS_0_VIOLATION_STATUS_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_VIOLATION_STATUS_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_SPARE 0x11fc  /*register offset*/
#define BPS_BPS_0_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PD2R_HW_VERSION 0x1200  /*register offset*/
#define BPS_BPS_0_CLC_PD2R_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_PD2R_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_PD2R_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_PD2R_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_PD2R_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_PD2R_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_PD2R_HW_STATUS 0x1204  /*register offset*/
#define BPS_BPS_0_CLC_PD2R_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_PD2R_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_PD2R_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PD2R_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PD2R_MODULE_CFG 0x1260  /*register offset*/
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_PACK_MODE_MASK 0x100
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_PACK_MODE_SHIFT 0x8
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_UNUSED1_MASK 0xfffffe00
#define BPS_BPS_0_CLC_PD2R_MODULE_CFG_UNUSED1_SHIFT 0x9

#define regBPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL 0x13f8  /*register offset*/
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_PD2R_SPARE 0x13fc  /*register offset*/
#define BPS_BPS_0_CLC_PD2R_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_PD2R_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_PD2R_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PD2R_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DEMUX_HW_VERSION 0x1400  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DEMUX_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMUX_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DEMUX_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DEMUX_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DEMUX_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DEMUX_HW_STATUS 0x1404  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_HW_STATUS_VIOLATION_CH_Y_MASK 0x1
#define BPS_BPS_0_CLC_DEMUX_HW_STATUS_VIOLATION_CH_Y_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMUX_HW_STATUS_VIOLATION_CH_UV_MASK 0x2
#define BPS_BPS_0_CLC_DEMUX_HW_STATUS_VIOLATION_CH_UV_SHIFT 0x1
#define BPS_BPS_0_CLC_DEMUX_HW_STATUS_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_DEMUX_HW_STATUS_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_DEMUX_MODULE_CFG 0x1460  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_PERIOD_MASK 0x700
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_PERIOD_SHIFT 0x8
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_UNUSED1_MASK 0xfffff800
#define BPS_BPS_0_CLC_DEMUX_MODULE_CFG_UNUSED1_SHIFT 0xb

#define regBPS_BPS_0_CLC_DEMUX_DEMUX_EVEN_LINE_CFG 0x1468  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_DEMUX_EVEN_LINE_CFG_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_CLC_DEMUX_DEMUX_EVEN_LINE_CFG_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_CLC_DEMUX_DEMUX_ODD_LINE_CFG 0x146c  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_DEMUX_ODD_LINE_CFG_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_CLC_DEMUX_DEMUX_ODD_LINE_CFG_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL 0x15f8  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_DEMUX_SPARE 0x15fc  /*register offset*/
#define BPS_BPS_0_CLC_DEMUX_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DEMUX_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMUX_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DEMUX_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PEDESTAL_HW_VERSION 0x1600  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_PEDESTAL_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_PEDESTAL_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_PEDESTAL_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_PEDESTAL_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_PEDESTAL_HW_STATUS 0x1604  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PEDESTAL_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_CFG 0x1608  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_ADDR_MASK 0xff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_UNUSED0_MASK 0xfff00
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_UNUSED0_SHIFT 0x8
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG 0x160c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_LUT_SEL_MASK 0x3
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA 0x1610  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_1 0x1614  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_2 0x1618  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_3 0x161c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_4 0x1620  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_5 0x1624  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_6 0x1628  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_7 0x162c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_8 0x1630  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_9 0x1634  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_10 0x1638  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_11 0x163c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_12 0x1640  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_13 0x1644  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_14 0x1648  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_DATA_15 0x164c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_CMD 0x1650  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_PEDESTAL_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_STATUS 0x1654  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PEDESTAL_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG 0x1658  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG 0x165c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_CFG 0x1660  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_SCALE_BYPASS_MASK 0x100
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_SCALE_BYPASS_SHIFT 0x8
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED1_MASK 0xe00
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED1_SHIFT 0x9
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_NUM_SUBBLOCKS_MASK 0x3000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_NUM_SUBBLOCKS_SHIFT 0xc
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED2_MASK 0xc000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED2_SHIFT 0xe
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_BLOCK_X_MASK 0xf0000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_BLOCK_X_SHIFT 0x10
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_BLOCK_Y_MASK 0xf00000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_BLOCK_Y_SHIFT 0x14
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_SUBBLOCK_X_MASK 0x7000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_SUBBLOCK_X_SHIFT 0x18
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED3_MASK 0x8000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED3_SHIFT 0x1b
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_SUBBLOCK_Y_MASK 0x70000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_INIT_SUBBLOCK_Y_SHIFT 0x1c
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED4_MASK 0x80000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG_UNUSED4_SHIFT 0x1f

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG 0x1668  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_BLOCK_WIDTH_MASK 0x7ff
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_BLOCK_WIDTH_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_BLOCK_HEIGHT_MASK 0x3ff0000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_BLOCK_HEIGHT_SHIFT 0x10
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG 0x166c  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_SUBBLOCK_WIDTH_MASK 0x7ff
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_SUBBLOCK_WIDTH_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_UNUSED0_MASK 0x800
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_INV_SUBBLOCK_WIDTH_MASK 0x1ffff000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_INV_SUBBLOCK_WIDTH_SHIFT 0xc
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG 0x1670  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_SUBBLOCK_HEIGHT_MASK 0x3ff
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_SUBBLOCK_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_UNUSED0_MASK 0xc00
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_INV_SUBBLOCK_HEIGHT_MASK 0x1ffff000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_INV_SUBBLOCK_HEIGHT_SHIFT 0xc
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG 0x1674  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_INIT_PIXEL_X_MASK 0x7ff
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_INIT_PIXEL_X_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_INIT_PIXEL_Y_MASK 0x3ff0000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_INIT_PIXEL_Y_SHIFT 0x10
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_PEDESTAL_MODULE_5_CFG 0x1678  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_5_CFG_INIT_YDELTA_MASK 0xfffff
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_5_CFG_INIT_YDELTA_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_5_CFG_UNUSED0_MASK 0xfff00000
#define BPS_BPS_0_CLC_PEDESTAL_MODULE_5_CFG_UNUSED0_SHIFT 0x14

#define regBPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL 0x17f8  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_PEDESTAL_SPARE 0x17fc  /*register offset*/
#define BPS_BPS_0_CLC_PEDESTAL_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_PEDESTAL_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_PEDESTAL_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_PEDESTAL_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_HW_VERSION 0x1800  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_LINEARIZATION_HW_STATUS 0x1804  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_CFG 0x1808  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_ADDR_MASK 0x3f
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_UNUSED0_MASK 0xfffc0
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_UNUSED0_SHIFT 0x6
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG 0x180c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_LUT_SEL_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA 0x1810  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_1 0x1814  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_2 0x1818  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_3 0x181c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_4 0x1820  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_5 0x1824  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_6 0x1828  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_7 0x182c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_8 0x1830  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_9 0x1834  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_10 0x1838  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_11 0x183c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_12 0x1840  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_13 0x1844  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_14 0x1848  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_15 0x184c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_CMD 0x1850  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_STATUS 0x1854  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG 0x1858  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG 0x185c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_MODULE_CFG 0x1860  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG 0x1868  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_P0_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_P0_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_P1_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_P1_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG 0x186c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_P2_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_P2_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_P3_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_P3_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG 0x1870  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_P4_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_P4_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_P5_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_P5_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG 0x1874  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_P6_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_P6_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_P7_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_P7_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG 0x1878  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_P0_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_P0_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_P1_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_P1_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG 0x187c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_P2_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_P2_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_P3_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_P3_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG 0x1880  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_P4_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_P4_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_P5_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_P5_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG 0x1884  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_P6_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_P6_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_P7_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_P7_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG 0x1888  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_P0_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_P0_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_P1_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_P1_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG 0x188c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_P2_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_P2_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_P3_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_P3_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG 0x1890  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_P4_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_P4_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_P5_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_P5_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG 0x1894  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_P6_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_P6_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_P7_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_P7_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG 0x1898  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_P0_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_P0_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_P1_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_P1_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG 0x189c  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_P2_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_P2_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_P3_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_P3_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG 0x18a0  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_P4_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_P4_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_P5_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_P5_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG 0x18a4  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_P6_MASK 0x3fff
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_P6_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_P7_MASK 0x3fff0000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_P7_SHIFT 0x10
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL 0x19f8  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_LINEARIZATION_SPARE 0x19fc  /*register offset*/
#define BPS_BPS_0_CLC_LINEARIZATION_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_LINEARIZATION_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_LINEARIZATION_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LINEARIZATION_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_BPC_PDPC_HW_VERSION 0x1a00  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_BPC_PDPC_HW_STATUS 0x1a04  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_OVERFLOW_ERROR_MASK 0x2
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_OVERFLOW_ERROR_SHIFT 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_OVERWRITE_MASK 0x4
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_OVERWRITE_SHIFT 0x2
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_CFG 0x1a08  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_ADDR_MASK 0x3f
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_UNUSED0_MASK 0xfffc0
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_UNUSED0_SHIFT 0x6
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG 0x1a0c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_LUT_SEL_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA 0x1a10  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_1 0x1a14  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_2 0x1a18  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_3 0x1a1c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_4 0x1a20  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_5 0x1a24  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_6 0x1a28  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_7 0x1a2c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_8 0x1a30  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_9 0x1a34  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_10 0x1a38  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_11 0x1a3c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_12 0x1a40  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_13 0x1a44  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_14 0x1a48  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_15 0x1a4c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_CMD 0x1a50  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_STATUS 0x1a54  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG 0x1a58  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG 0x1a5c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG 0x1a60  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_UNUSED0_MASK 0xfc
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_PDAF_PDPC_EN_MASK 0x100
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_PDAF_PDPC_EN_SHIFT 0x8
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_BPC_EN_MASK 0x200
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_BPC_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_LEFT_CROP_EN_MASK 0x400
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_LEFT_CROP_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_RIGHT_CROP_EN_MASK 0x800
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_RIGHT_CROP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_HOT_PIXEL_CORRECTION_DISABLE_MASK 0x1000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_HOT_PIXEL_CORRECTION_DISABLE_SHIFT 0xc
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_COLD_PIXEL_CORRECTION_DISABLE_MASK 0x2000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_COLD_PIXEL_CORRECTION_DISABLE_SHIFT 0xd
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_USING_CROSS_CHANNEL_EN_MASK 0x4000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_USING_CROSS_CHANNEL_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_REMOVE_ALONG_EDGE_EN_MASK 0x8000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_REMOVE_ALONG_EDGE_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_BAYER_PATTERN_MASK 0x30000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_BAYER_PATTERN_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_PDAF_HDR_SELECTION_MASK 0x1c0000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_PDAF_HDR_SELECTION_SHIFT 0x12
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_PDAF_ZZHDR_FIRST_RB_EXP_MASK 0x200000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_PDAF_ZZHDR_FIRST_RB_EXP_SHIFT 0x15
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_CHANNEL_BALANCE_EN_MASK 0x400000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_CHANNEL_BALANCE_EN_SHIFT 0x16
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_BPC_PDPC_PDPC_BLACK_LEVEL 0x1a68  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDPC_BLACK_LEVEL_BLACK_LEVEL_MASK 0xfff
#define BPS_BPS_0_CLC_BPC_PDPC_PDPC_BLACK_LEVEL_BLACK_LEVEL_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDPC_BLACK_LEVEL_UNUSED0_MASK 0xfffff000
#define BPS_BPS_0_CLC_BPC_PDPC_PDPC_BLACK_LEVEL_UNUSED0_SHIFT 0xc

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO 0x1a6c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_EXP_RATIO_RECIP_MASK 0x1ff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_EXP_RATIO_RECIP_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_EXP_RATIO_MASK 0x7fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_EXP_RATIO_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS 0x1a70  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_FMIN_PIXEL_Q6_MASK 0xff
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_FMIN_PIXEL_Q6_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_FMAX_PIXEL_Q6_MASK 0xff00
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_FMAX_PIXEL_Q6_SHIFT 0x8
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_CORRECTION_THRESHOLD_MASK 0x3fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_CORRECTION_THRESHOLD_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET 0x1a74  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_BPC_OFFSET_MASK 0x3fff
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_BPC_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_BCC_OFFSET_MASK 0x3fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_BCC_OFFSET_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_RG_WB_GAIN 0x1a78  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_RG_WB_GAIN_RG_WB_GAIN_MASK 0x1ffff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_RG_WB_GAIN_RG_WB_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_RG_WB_GAIN_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_RG_WB_GAIN_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_BG_WB_GAIN 0x1a7c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_BG_WB_GAIN_BG_WB_GAIN_MASK 0x1ffff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_BG_WB_GAIN_BG_WB_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_BG_WB_GAIN_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_BG_WB_GAIN_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_GR_WB_GAIN 0x1a80  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GR_WB_GAIN_GR_WB_GAIN_MASK 0x1ffff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GR_WB_GAIN_GR_WB_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GR_WB_GAIN_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GR_WB_GAIN_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_GB_WB_GAIN 0x1a84  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GB_WB_GAIN_GB_WB_GAIN_MASK 0x1ffff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GB_WB_GAIN_GB_WB_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GB_WB_GAIN_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_GB_WB_GAIN_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG 0x1a88  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_X_OFFSET_MASK 0x3fff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_X_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_Y_OFFSET_MASK 0x3fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_Y_OFFSET_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG 0x1a8c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_X_END_MASK 0x3fff
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_X_END_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_Y_END_MASK 0x3fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_Y_END_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG 0x1a90  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_PERIOD_MASK 0x7
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_PERIOD_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_BLK_OUT_MASK 0xfff0
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_BLK_OUT_SHIFT 0x4
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_UNUSED1_MASK 0xf0000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_UNUSED1_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_BLK_IN_MASK 0xfff00000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG_BLK_IN_SHIFT 0x14

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0 0x1a94  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_CH0_GAIN_EVEN_MASK 0x7fff
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_CH0_GAIN_EVEN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_CH0_GAIN_ODD_MASK 0x7fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_CH0_GAIN_ODD_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12 0x1a98  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_CH1_GAIN_MASK 0x7fff
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_CH1_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_CH2_GAIN_MASK 0x7fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_CH2_GAIN_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0 0x1a9c  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_CH0_GAIN_EVEN_MASK 0x7fff
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_CH0_GAIN_EVEN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_CH0_GAIN_ODD_MASK 0x7fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_CH0_GAIN_ODD_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12 0x1aa0  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_CH1_GAIN_MASK 0x7fff
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_CH1_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_CH2_GAIN_MASK 0x7fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_CH2_GAIN_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_EVEN_CFG 0x1aa4  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_EVEN_CFG_EVEN_LINE_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_EVEN_CFG_EVEN_LINE_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_DEMUX_ODD_CFG 0x1aa8  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_ODD_CFG_ODD_LINE_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_CLC_BPC_PDPC_DEMUX_ODD_CFG_ODD_LINE_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2 0x1aac  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_BPC_OFFSET_T2_MASK 0x3fff
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_BPC_OFFSET_T2_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_BCC_OFFSET_T2_MASK 0x3fff0000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_BCC_OFFSET_T2_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_BPC_PDPC_SATURATION_THRESHOLD 0x1ab0  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_SATURATION_THRESHOLD_SAT_THRESHOLD_MASK 0x3fff
#define BPS_BPS_0_CLC_BPC_PDPC_SATURATION_THRESHOLD_SAT_THRESHOLD_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_SATURATION_THRESHOLD_UNUSED0_MASK 0xffffc000
#define BPS_BPS_0_CLC_BPC_PDPC_SATURATION_THRESHOLD_UNUSED0_SHIFT 0xe

#define regBPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG 0x1ab4  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_X_OFFSET_MASK 0x1f
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_X_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_UNUSED0_MASK 0xffe0
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_UNUSED0_SHIFT 0x5
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_Y_OFFSET_MASK 0x3f0000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_Y_OFFSET_SHIFT 0x10
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_UNUSED1_MASK 0xffc00000
#define BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG_UNUSED1_SHIFT 0x16

#define regBPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL 0x1bf8  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_BPC_PDPC_SPARE 0x1bfc  /*register offset*/
#define BPS_BPS_0_CLC_BPC_PDPC_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_BPC_PDPC_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_BPC_PDPC_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_BPC_PDPC_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HDR_RECON_HW_VERSION 0x1c00  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_HDR_RECON_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_HDR_RECON_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_RECON_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_HDR_RECON_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HDR_RECON_HW_STATUS 0x1c04  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_HDR_RECON_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HDR_RECON_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HDR_RECON_MODULE_CFG 0x1c60  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG 0x1c68  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_ZREC_ENABLE_MASK 0x1
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_ZREC_ENABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_RECON_LINEAR_MODE_MASK 0x2
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_RECON_LINEAR_MODE_SHIFT 0x1
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_EXP_RATIO_MASK 0x1fffc
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_EXP_RATIO_SHIFT 0x2
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_HDR_RECON_HDR_1_CFG 0x1c6c  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_HDR_1_CFG_RG_WB_GAIN_RATIO_MASK 0x1ffff
#define BPS_BPS_0_CLC_HDR_RECON_HDR_1_CFG_RG_WB_GAIN_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_HDR_1_CFG_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_HDR_RECON_HDR_1_CFG_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_HDR_RECON_HDR_2_CFG 0x1c70  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_HDR_2_CFG_BG_WB_GAIN_RATIO_MASK 0x1ffff
#define BPS_BPS_0_CLC_HDR_RECON_HDR_2_CFG_BG_WB_GAIN_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_HDR_2_CFG_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_HDR_RECON_HDR_2_CFG_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_HDR_RECON_HDR_3_CFG 0x1c74  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_HDR_3_CFG_BLK_IN_MASK 0xff
#define BPS_BPS_0_CLC_HDR_RECON_HDR_3_CFG_BLK_IN_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_HDR_3_CFG_UNUSED0_MASK 0xffffff00
#define BPS_BPS_0_CLC_HDR_RECON_HDR_3_CFG_UNUSED0_SHIFT 0x8

#define regBPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG 0x1c78  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_MOTION_DTH_LOG2_MASK 0xf
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_MOTION_DTH_LOG2_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_UNUSED0_MASK 0x10
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_MOTION_TH1_MASK 0x7fe0
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_MOTION_TH1_SHIFT 0x5
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_UNUSED1_MASK 0x8000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_UNUSED1_SHIFT 0xf
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_H_EDGE_DTH_LOG2_MASK 0xf0000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_H_EDGE_DTH_LOG2_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_H_EDGE_TH1_MASK 0x3ff00000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_RECON_H_EDGE_TH1_SHIFT 0x14
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_UNUSED2_MASK 0xc0000000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG_UNUSED2_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG 0x1c7c  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_EDGE_LPF_TAP0_MASK 0x7
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_EDGE_LPF_TAP0_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_FLAT_REGION_TH_MASK 0x3ff0
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_FLAT_REGION_TH_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED1_MASK 0x4000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_DARK_DTH_LOG2_MASK 0x38000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_DARK_DTH_LOG2_SHIFT 0xf
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED2_MASK 0x40000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED2_SHIFT 0x12
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_DARK_TH1_MASK 0x1ff80000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_DARK_TH1_SHIFT 0x13
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED3_MASK 0x20000000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED3_SHIFT 0x1d
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_FIRST_FIELD_MASK 0x40000000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_RECON_FIRST_FIELD_SHIFT 0x1e
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED4_MASK 0x80000000
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG_UNUSED4_SHIFT 0x1f

#define regBPS_BPS_0_CLC_HDR_RECON_IHDR_2_CFG 0x1c80  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_2_CFG_RECON_MIN_FACTOR_MASK 0x1f
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_2_CFG_RECON_MIN_FACTOR_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_2_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_CLC_HDR_RECON_IHDR_2_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG 0x1c84  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_ZREC_PREFILT_TAP0_MASK 0x7f
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_ZREC_PREFILT_TAP0_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_UNUSED0_MASK 0x80
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_UNUSED0_SHIFT 0x7
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_ZREC_PATTERN_MASK 0x300
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_ZREC_PATTERN_SHIFT 0x8
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_UNUSED1_MASK 0x400
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_UNUSED1_SHIFT 0xa
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_ZREC_FIRST_RB_EXP_MASK 0x800
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_ZREC_FIRST_RB_EXP_SHIFT 0xb
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_UNUSED2_MASK 0xfffff000
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG_UNUSED2_SHIFT 0xc

#define regBPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG 0x1c88  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_RB_DTH_LOG2_MASK 0xf
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_RB_DTH_LOG2_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_RB_GRAD_TH1_MASK 0xfff0
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_RB_GRAD_TH1_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_G_DTH_LOG2_MASK 0xf0000
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_G_DTH_LOG2_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_G_GRAD_TH1_MASK 0xfff00000
#define BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG_ZREC_G_GRAD_TH1_SHIFT 0x14

#define regBPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL 0x1df8  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_HDR_RECON_SPARE 0x1dfc  /*register offset*/
#define BPS_BPS_0_CLC_HDR_RECON_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_HDR_RECON_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_RECON_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HDR_RECON_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HDR_MAC_HW_VERSION 0x1e00  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_HDR_MAC_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_HDR_MAC_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_MAC_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_HDR_MAC_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HDR_MAC_HW_STATUS 0x1e04  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_HDR_MAC_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HDR_MAC_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HDR_MAC_MODULE_CFG 0x1e60  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG 0x1e68  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_EXP_RATIO_MASK 0x7fff
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_EXP_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_EXP_RATIO_RECIP_MASK 0x1ff0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_EXP_RATIO_RECIP_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG 0x1e6c  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_GB_WB_GAIN_RATIO_MASK 0x1ffff
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_GB_WB_GAIN_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_UNUSED0_MASK 0xe0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_UNUSED0_SHIFT 0x11
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_BLK_IN_MASK 0xff00000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_BLK_IN_SHIFT 0x14
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG 0x1e70  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG_GR_WB_GAIN_RATIO_MASK 0x1ffff
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG_GR_WB_GAIN_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG_UNUSED0_MASK 0xe0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG_UNUSED0_SHIFT 0x11
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG_BLK_OUT_MASK 0xfff00000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG_BLK_OUT_SHIFT 0x14

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG 0x1e74  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_MAC_MOTION_0_TH1_MASK 0x3ff
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_MAC_MOTION_0_TH1_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_MAC_MOTION_0_TH2_MASK 0xff0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_MAC_MOTION_0_TH2_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_MAC_SQRT_ANALOG_GAIN_MASK 0x7f000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_MAC_SQRT_ANALOG_GAIN_SHIFT 0x18
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG 0x1e78  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_DILATION_MASK 0x7
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_DILATION_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_LOW_LIGHT_DTH_LOG2_MASK 0xf0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_LOW_LIGHT_DTH_LOG2_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_MOTION_0_DT0_MASK 0x3f00
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_MOTION_0_DT0_SHIFT 0x8
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_MOTION_STRENGTH_MASK 0x1f0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_MOTION_STRENGTH_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED2_MASK 0xe00000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED2_SHIFT 0x15
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_LOW_LIGHT_STRENGTH_MASK 0x1f000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_MAC_LOW_LIGHT_STRENGTH_SHIFT 0x18
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED3_MASK 0xe0000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG_UNUSED3_SHIFT 0x1d

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG 0x1e7c  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_MAC_LOW_LIGHT_TH1_MASK 0x3fff
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_MAC_LOW_LIGHT_TH1_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_MAC_HIGH_LIGHT_TH1_MASK 0x3fff0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_MAC_HIGH_LIGHT_TH1_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG 0x1e80  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_HIGH_LIGHT_DTH_LOG2_MASK 0xf
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_HIGH_LIGHT_DTH_LOG2_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_TH1_MASK 0x1ff0
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_TH1_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_DTH_LOG2_MASK 0xf0000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_DTH_LOG2_SHIFT 0x10
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_TAP0_MASK 0x700000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_TAP0_SHIFT 0x14
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_UNUSED1_MASK 0x800000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_UNUSED1_SHIFT 0x17
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_ENABLE_MASK 0x1000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_SMOOTH_ENABLE_SHIFT 0x18
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MSB_ALIGNED_MASK 0x2000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MSB_ALIGNED_SHIFT 0x19
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_LINEAR_MODE_MASK 0x4000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_MAC_LINEAR_MODE_SHIFT 0x1a
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_UNUSED2_MASK 0xf8000000
#define BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG_UNUSED2_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL 0x1ff8  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_HDR_MAC_SPARE 0x1ffc  /*register offset*/
#define BPS_BPS_0_CLC_HDR_MAC_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_HDR_MAC_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_HDR_MAC_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HDR_MAC_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GIC_HW_VERSION 0x2000  /*register offset*/
#define BPS_BPS_0_CLC_GIC_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_GIC_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_GIC_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_GIC_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_GIC_HW_STATUS 0x2004  /*register offset*/
#define BPS_BPS_0_CLC_GIC_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_GIC_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GIC_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GIC_DMI_CFG 0x2008  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_CFG_ADDR_MASK 0x3f
#define BPS_BPS_0_CLC_GIC_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_DMI_CFG_UNUSED0_MASK 0xfffc0
#define BPS_BPS_0_CLC_GIC_DMI_CFG_UNUSED0_SHIFT 0x6
#define BPS_BPS_0_CLC_GIC_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_GIC_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_GIC_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_GIC_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_GIC_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_GIC_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_GIC_DMI_LUT_CFG 0x200c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_LUT_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GIC_DMI_DATA 0x2010  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_1 0x2014  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_2 0x2018  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_3 0x201c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_4 0x2020  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_5 0x2024  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_6 0x2028  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_7 0x202c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_8 0x2030  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_9 0x2034  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_10 0x2038  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_11 0x203c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_12 0x2040  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_13 0x2044  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_14 0x2048  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_DATA_15 0x204c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GIC_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GIC_DMI_CMD 0x2050  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_GIC_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_GIC_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_GIC_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_GIC_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_GIC_DMI_STATUS 0x2054  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_GIC_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GIC_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG 0x2058  /*register offset*/
#define BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG 0x205c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GIC_MODULE_CFG 0x2060  /*register offset*/
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_UNUSED0_MASK 0xfc
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_PNR_EN_MASK 0x100
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_PNR_EN_SHIFT 0x8
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_GIC_EN_MASK 0x200
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_GIC_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_UNUSED1_MASK 0xfffffc00
#define BPS_BPS_0_CLC_GIC_MODULE_CFG_UNUSED1_SHIFT 0xa

#define regBPS_BPS_0_CLC_GIC_GIC_FILTER_CFG 0x2070  /*register offset*/
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_GIC_FILTER_STRENGTH_MASK 0x1ff
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_GIC_FILTER_STRENGTH_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_GIC_NOISE_SCALE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_GIC_NOISE_SCALE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_THIN_LINE_NOISE_OFFSET 0x2074  /*register offset*/
#define BPS_BPS_0_CLC_GIC_THIN_LINE_NOISE_OFFSET_VALUE_MASK 0x3fff
#define BPS_BPS_0_CLC_GIC_THIN_LINE_NOISE_OFFSET_VALUE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_THIN_LINE_NOISE_OFFSET_UNUSED0_MASK 0xffffc000
#define BPS_BPS_0_CLC_GIC_THIN_LINE_NOISE_OFFSET_UNUSED0_SHIFT 0xe

#define regBPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0 0x2078  /*register offset*/
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_BASE_TABLE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_BASE_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_ANCHOR_TABLE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_ANCHOR_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1 0x207c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_BASE_TABLE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_BASE_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_ANCHOR_TABLE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_ANCHOR_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2 0x2080  /*register offset*/
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_BASE_TABLE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_BASE_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_ANCHOR_TABLE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_ANCHOR_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3 0x2084  /*register offset*/
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_BASE_TABLE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_BASE_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_ANCHOR_TABLE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_ANCHOR_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4 0x2088  /*register offset*/
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_BASE_TABLE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_BASE_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_ANCHOR_TABLE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_ANCHOR_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5 0x208c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_BASE_TABLE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_BASE_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_ANCHOR_TABLE_MASK 0x3ff0000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_ANCHOR_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0 0x2090  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_SHIFT_TABLE_MASK 0xf
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_SHIFT_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_SLOPE_TABLE_MASK 0x7ff0000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_SLOPE_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1 0x2094  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_SHIFT_TABLE_MASK 0xf
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_SHIFT_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_SLOPE_TABLE_MASK 0x7ff0000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_SLOPE_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2 0x2098  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_SHIFT_TABLE_MASK 0xf
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_SHIFT_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_SLOPE_TABLE_MASK 0x7ff0000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_SLOPE_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3 0x209c  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_SHIFT_TABLE_MASK 0xf
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_SHIFT_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_SLOPE_TABLE_MASK 0x7ff0000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_SLOPE_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4 0x20a0  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_SHIFT_TABLE_MASK 0xf
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_SHIFT_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_SLOPE_TABLE_MASK 0x7ff0000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_SLOPE_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5 0x20a4  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_SHIFT_TABLE_MASK 0xf
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_SHIFT_TABLE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_SLOPE_TABLE_MASK 0x7ff0000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_SLOPE_TABLE_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_GIC_INIT_HV_OFFSET 0x20a8  /*register offset*/
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_BY_MASK 0x3fff
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_BY_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_BX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_BX_SHIFT 0x10
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_GIC_R_SQUARE_INIT 0x20ac  /*register offset*/
#define BPS_BPS_0_CLC_GIC_R_SQUARE_INIT_VALUE_MASK 0xfffffff
#define BPS_BPS_0_CLC_GIC_R_SQUARE_INIT_VALUE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_R_SQUARE_INIT_UNUSED0_MASK 0xf0000000
#define BPS_BPS_0_CLC_GIC_R_SQUARE_INIT_UNUSED0_SHIFT 0x1c

#define regBPS_BPS_0_CLC_GIC_R_SCALE_SHIFT 0x20b0  /*register offset*/
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_R_SQUARE_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_R_SQUARE_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_UNUSED0_MASK 0xf0
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_R_SQUARE_SCALE_MASK 0x7f00
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_R_SQUARE_SCALE_SHIFT 0x8
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_UNUSED1_MASK 0xffff8000
#define BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT_UNUSED1_SHIFT 0xf

#define regBPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_0 0x20b4  /*register offset*/
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_0_R_SQUARE_SCALE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_0_R_SQUARE_SCALE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_0_UNUSED0_MASK 0xfffffc00
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_0_UNUSED0_SHIFT 0xa

#define regBPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_1 0x20b8  /*register offset*/
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_1_R_SQUARE_SCALE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_1_R_SQUARE_SCALE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_1_UNUSED0_MASK 0xfffffc00
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_1_UNUSED0_SHIFT 0xa

#define regBPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_2 0x20bc  /*register offset*/
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_2_R_SQUARE_SCALE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_2_R_SQUARE_SCALE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_2_UNUSED0_MASK 0xfffffc00
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_2_UNUSED0_SHIFT 0xa

#define regBPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_3 0x20c0  /*register offset*/
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_3_R_SQUARE_SCALE_MASK 0x3ff
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_3_R_SQUARE_SCALE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_3_UNUSED0_MASK 0xfffffc00
#define BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_3_UNUSED0_SHIFT 0xa

#define regBPS_BPS_0_CLC_GIC_PNR_FILTER_STRENGTH 0x20c4  /*register offset*/
#define BPS_BPS_0_CLC_GIC_PNR_FILTER_STRENGTH_VALUE_MASK 0x1ff
#define BPS_BPS_0_CLC_GIC_PNR_FILTER_STRENGTH_VALUE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_PNR_FILTER_STRENGTH_UNUSED0_MASK 0xfffffe00
#define BPS_BPS_0_CLC_GIC_PNR_FILTER_STRENGTH_UNUSED0_SHIFT 0x9

#define regBPS_BPS_0_CLC_GIC_SPARE 0x21fc  /*register offset*/
#define BPS_BPS_0_CLC_GIC_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_GIC_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_GIC_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GIC_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_ABF_HW_VERSION 0x2200  /*register offset*/
#define BPS_BPS_0_CLC_ABF_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_ABF_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_HW_STATUS 0x2204  /*register offset*/
#define BPS_BPS_0_CLC_ABF_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_ABF_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_ABF_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_ABF_DMI_CFG 0x2208  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_CFG_ADDR_MASK 0xff
#define BPS_BPS_0_CLC_ABF_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_DMI_CFG_UNUSED0_MASK 0xfff00
#define BPS_BPS_0_CLC_ABF_DMI_CFG_UNUSED0_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_ABF_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_ABF_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_ABF_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_ABF_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_ABF_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_ABF_DMI_LUT_CFG 0x220c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_MASK 0x7
#define BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_ABF_DMI_DATA 0x2210  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_1 0x2214  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_2 0x2218  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_3 0x221c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_4 0x2220  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_5 0x2224  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_6 0x2228  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_7 0x222c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_8 0x2230  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_9 0x2234  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_10 0x2238  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_11 0x223c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_12 0x2240  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_13 0x2244  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_14 0x2248  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_DATA_15 0x224c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_ABF_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_ABF_DMI_CMD 0x2250  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_ABF_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_ABF_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_ABF_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_ABF_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_ABF_DMI_STATUS 0x2254  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_ABF_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_ABF_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG 0x2258  /*register offset*/
#define BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG 0x225c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_ABF_MODULE_CFG 0x2260  /*register offset*/
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED0_MASK 0xfc
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_FILTER_EN_MASK 0x100
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_FILTER_EN_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_ACT_ADJ_EN_MASK 0x200
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_ACT_ADJ_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_DARK_SMOOTH_EN_MASK 0x400
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_DARK_SMOOTH_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_DARK_DESAT_EN_MASK 0x800
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_DARK_DESAT_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_DIR_SMOOTH_EN_MASK 0x1000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_DIR_SMOOTH_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_MINMAX_EN_MASK 0x2000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_MINMAX_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_CROSS_PLANE_EN_MASK 0x4000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_CROSS_PLANE_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_BLS_EN_MASK 0x8000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_BLS_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_PIX_MATCH_LEVEL_RB_MASK 0x70000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_PIX_MATCH_LEVEL_RB_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED1_MASK 0x80000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED1_SHIFT 0x13
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_PIX_MATCH_LEVEL_G_MASK 0x700000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_PIX_MATCH_LEVEL_G_SHIFT 0x14
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED2_MASK 0x800000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED2_SHIFT 0x17
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_BLOCK_MATCH_PATTERN_RB_MASK 0x3000000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_BLOCK_MATCH_PATTERN_RB_SHIFT 0x18
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED3_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_MODULE_CFG_UNUSED3_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_0_CFG 0x2268  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_EDGE_SOFTNESS_GR_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_EDGE_SOFTNESS_GR_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_EDGE_SOFTNESS_GB_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_EDGE_SOFTNESS_GB_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_0_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_1_CFG 0x226c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_EDGE_SOFTNESS_R_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_EDGE_SOFTNESS_R_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_EDGE_SOFTNESS_B_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_EDGE_SOFTNESS_B_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_1_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_2_CFG 0x2270  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL0_GRGB_0_MASK 0x7
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL0_GRGB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL0_GRGB_1_MASK 0x30
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL0_GRGB_1_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL0_GRGB_2_MASK 0x40
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL0_GRGB_2_SHIFT 0x6
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED1_MASK 0x80
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED1_SHIFT 0x7
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL1_GRGB_0_MASK 0x700
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL1_GRGB_0_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED2_MASK 0x800
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED2_SHIFT 0xb
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL1_GRGB_1_MASK 0x3000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL1_GRGB_1_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL1_GRGB_2_MASK 0x4000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL1_GRGB_2_SHIFT 0xe
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED3_MASK 0x8000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED3_SHIFT 0xf
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL2_GRGB_0_MASK 0x70000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL2_GRGB_0_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED4_MASK 0x80000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED4_SHIFT 0x13
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL2_GRGB_1_MASK 0x300000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL2_GRGB_1_SHIFT 0x14
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL2_GRGB_2_MASK 0x400000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_DISTANCE_LEVEL2_GRGB_2_SHIFT 0x16
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED5_MASK 0xff800000
#define BPS_BPS_0_CLC_ABF_ABF_2_CFG_UNUSED5_SHIFT 0x17

#define regBPS_BPS_0_CLC_ABF_ABF_3_CFG 0x2274  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL0_RB_0_MASK 0x7
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL0_RB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL0_RB_1_MASK 0x30
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL0_RB_1_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL0_RB_2_MASK 0x40
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL0_RB_2_SHIFT 0x6
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED1_MASK 0x80
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED1_SHIFT 0x7
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL1_RB_0_MASK 0x700
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL1_RB_0_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED2_MASK 0x800
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED2_SHIFT 0xb
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL1_RB_1_MASK 0x3000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL1_RB_1_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL1_RB_2_MASK 0x4000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL1_RB_2_SHIFT 0xe
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED3_MASK 0x8000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED3_SHIFT 0xf
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL2_RB_0_MASK 0x70000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL2_RB_0_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED4_MASK 0x80000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED4_SHIFT 0x13
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL2_RB_1_MASK 0x300000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL2_RB_1_SHIFT 0x14
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL2_RB_2_MASK 0x400000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_DISTANCE_LEVEL2_RB_2_SHIFT 0x16
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED5_MASK 0xff800000
#define BPS_BPS_0_CLC_ABF_ABF_3_CFG_UNUSED5_SHIFT 0x17

#define regBPS_BPS_0_CLC_ABF_ABF_4_CFG 0x2278  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_GR_MASK 0x7f
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_GR_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED0_MASK 0x80
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED0_SHIFT 0x7
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_R_MASK 0x7f00
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_R_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED1_MASK 0x8000
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED1_SHIFT 0xf
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_B_MASK 0x7f0000
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_B_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED2_MASK 0x800000
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED2_SHIFT 0x17
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_GB_MASK 0x7f000000
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_CURVE_OFFSET_GB_SHIFT 0x18
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED3_MASK 0x80000000
#define BPS_BPS_0_CLC_ABF_ABF_4_CFG_UNUSED3_SHIFT 0x1f

#define regBPS_BPS_0_CLC_ABF_ABF_5_CFG 0x227c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_FILTER_STRENGTH_GR_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_FILTER_STRENGTH_GR_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_FILTER_STRENGTH_R_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_FILTER_STRENGTH_R_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_5_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_6_CFG 0x2280  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_FILTER_STRENGTH_GB_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_FILTER_STRENGTH_GB_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_FILTER_STRENGTH_B_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_FILTER_STRENGTH_B_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_6_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_7_CFG 0x2284  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_MAX_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_MAX_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_OFFSET_MASK 0xfff0
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_OFFSET_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_MIN_SHIFT_MASK 0xf0000
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_MIN_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_BLS_MASK 0xfff00000
#define BPS_BPS_0_CLC_ABF_ABF_7_CFG_MINMAX_BLS_SHIFT 0x14

#define regBPS_BPS_0_CLC_ABF_ABF_8_CFG 0x2288  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_RNR_BX_MASK 0x3fff
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_RNR_BX_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_RNR_BY_MASK 0x3fff0000
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_RNR_BY_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_ABF_ABF_8_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_ABF_ABF_9_CFG 0x228c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_9_CFG_RNR_INIT_RSQUARE_MASK 0xfffffff
#define BPS_BPS_0_CLC_ABF_ABF_9_CFG_RNR_INIT_RSQUARE_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_9_CFG_UNUSED0_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_9_CFG_UNUSED0_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_10_CFG 0x2290  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_10_CFG_RNR_RSQUARE_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_ABF_ABF_10_CFG_RNR_RSQUARE_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_10_CFG_RNR_RSQUARE_SCALE_MASK 0x7f0
#define BPS_BPS_0_CLC_ABF_ABF_10_CFG_RNR_RSQUARE_SCALE_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_10_CFG_UNUSED0_MASK 0xfffff800
#define BPS_BPS_0_CLC_ABF_ABF_10_CFG_UNUSED0_SHIFT 0xb

#define regBPS_BPS_0_CLC_ABF_ABF_11_CFG 0x2294  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_RNR_ANCHOR_0_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_RNR_ANCHOR_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_RNR_ANCHOR_1_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_RNR_ANCHOR_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_11_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_12_CFG 0x2298  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_RNR_ANCHOR_2_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_RNR_ANCHOR_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_RNR_ANCHOR_3_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_RNR_ANCHOR_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_12_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_13_CFG 0x229c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_RNR_NOISE_BASE_0_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_RNR_NOISE_BASE_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_RNR_NOISE_BASE_1_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_RNR_NOISE_BASE_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_13_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_14_CFG 0x22a0  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_RNR_NOISE_BASE_2_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_RNR_NOISE_BASE_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_RNR_NOISE_BASE_3_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_RNR_NOISE_BASE_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_14_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_15_CFG 0x22a4  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_RNR_NOISE_SLOPE_0_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_RNR_NOISE_SLOPE_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_RNR_NOISE_SLOPE_1_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_RNR_NOISE_SLOPE_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_15_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_16_CFG 0x22a8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_RNR_NOISE_SLOPE_2_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_RNR_NOISE_SLOPE_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_RNR_NOISE_SLOPE_3_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_RNR_NOISE_SLOPE_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_16_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_17_CFG 0x22ac  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_0_MASK 0xf
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_1_MASK 0xf0
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_1_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_2_MASK 0xf00
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_2_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_3_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_NOISE_SHIFT_3_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_0_MASK 0xf0000
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_0_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_1_MASK 0xf00000
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_1_SHIFT 0x14
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_2_MASK 0xf000000
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_2_SHIFT 0x18
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_3_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_17_CFG_RNR_THRESH_SHIFT_3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_18_CFG 0x22b0  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_RNR_THRESH_BASE_0_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_RNR_THRESH_BASE_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_RNR_THRESH_BASE_1_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_RNR_THRESH_BASE_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_18_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_19_CFG 0x22b4  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_RNR_THRESH_BASE_2_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_RNR_THRESH_BASE_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_RNR_THRESH_BASE_3_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_RNR_THRESH_BASE_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_19_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_20_CFG 0x22b8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_RNR_THRESH_SLOPE_0_MASK 0x3ff
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_RNR_THRESH_SLOPE_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_RNR_THRESH_SLOPE_1_MASK 0x3ff0000
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_RNR_THRESH_SLOPE_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_ABF_20_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_21_CFG 0x22bc  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_RNR_THRESH_SLOPE_2_MASK 0x3ff
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_RNR_THRESH_SLOPE_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_RNR_THRESH_SLOPE_3_MASK 0x3ff0000
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_RNR_THRESH_SLOPE_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_ABF_21_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_22_CFG 0x22c0  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_NP_ANCHOR_0_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_NP_ANCHOR_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_NP_ANCHOR_1_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_NP_ANCHOR_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_22_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_23_CFG 0x22c4  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_NP_ANCHOR_2_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_NP_ANCHOR_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_NP_ANCHOR_3_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_NP_ANCHOR_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_23_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_24_CFG 0x22c8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_NP_BASE_RB_0_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_NP_BASE_RB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_NP_BASE_RB_1_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_NP_BASE_RB_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_24_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_25_CFG 0x22cc  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_NP_BASE_RB_2_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_NP_BASE_RB_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_NP_BASE_RB_3_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_NP_BASE_RB_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_25_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_26_CFG 0x22d0  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_NP_SLOPE_RB_0_MASK 0x3ff
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_NP_SLOPE_RB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_NP_SLOPE_RB_1_MASK 0x3ff0000
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_NP_SLOPE_RB_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_ABF_26_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_27_CFG 0x22d4  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_NP_SLOPE_RB_2_MASK 0x3ff
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_NP_SLOPE_RB_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_NP_SLOPE_RB_3_MASK 0x3ff0000
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_NP_SLOPE_RB_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_ABF_27_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_28_CFG 0x22d8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_0_MASK 0xf
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_1_MASK 0xf0
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_1_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_2_MASK 0xf00
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_2_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_3_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_RB_3_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_0_MASK 0xf0000
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_0_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_1_MASK 0xf00000
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_1_SHIFT 0x14
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_2_MASK 0xf000000
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_2_SHIFT 0x18
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_3_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_28_CFG_NP_SHIFT_GRGB_3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_29_CFG 0x22dc  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_NP_BASE_GRGB_0_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_NP_BASE_GRGB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_NP_BASE_GRGB_1_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_NP_BASE_GRGB_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_29_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_30_CFG 0x22e0  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_NP_BASE_GRGB_2_MASK 0x1ff
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_NP_BASE_GRGB_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_NP_BASE_GRGB_3_MASK 0x1ff0000
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_NP_BASE_GRGB_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_ABF_ABF_30_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_ABF_ABF_31_CFG 0x22e4  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_NP_SLOPE_GRGB_0_MASK 0x3ff
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_NP_SLOPE_GRGB_0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_NP_SLOPE_GRGB_1_MASK 0x3ff0000
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_NP_SLOPE_GRGB_1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_ABF_31_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_32_CFG 0x22e8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_NP_SLOPE_GRGB_2_MASK 0x3ff
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_NP_SLOPE_GRGB_2_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_NP_SLOPE_GRGB_3_MASK 0x3ff0000
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_NP_SLOPE_GRGB_3_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_ABF_ABF_32_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_ABF_ABF_33_CFG 0x22ec  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_ACT_FAC0_MASK 0x1fff
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_ACT_FAC0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_ACT_FAC1_MASK 0x1fff0000
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_ACT_FAC1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_ABF_ABF_33_CFG_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_ABF_ABF_34_CFG 0x22f0  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_ACT_THD0_MASK 0x1fff
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_ACT_THD0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_ACT_THD1_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_ACT_THD1_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_34_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_35_CFG 0x22f4  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_ACT_SMOOTH_THD0_MASK 0xff
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_ACT_SMOOTH_THD0_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_ACT_SMOOTH_THD1_MASK 0xff00
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_ACT_SMOOTH_THD1_SHIFT 0x8
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_DARK_THD_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_DARK_THD_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_UNUSED0_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_35_CFG_UNUSED0_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_36_CFG 0x22f8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_GR_RATIO_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_GR_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_RG_RATIO_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_RG_RATIO_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_36_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_37_CFG 0x22fc  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_GB_RATIO_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_GB_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_BG_RATIO_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_BG_RATIO_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_37_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_38_CFG 0x2300  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_RB_RATIO_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_RB_RATIO_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_BR_RATIO_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_BR_RATIO_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_38_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_39_CFG 0x2304  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_DETECT_THD_MASK 0xf
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_DETECT_THD_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_DETECT_NOISE_SCALAR_MASK 0xfff0
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_DETECT_NOISE_SCALAR_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_COUNT_THD_MASK 0x1f0000
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_COUNT_THD_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_UNUSED0_MASK 0xe00000
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_UNUSED0_SHIFT 0x15
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_SMOOTH_STRENGTH_MASK 0x7f000000
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_EDGE_SMOOTH_STRENGTH_SHIFT 0x18
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_ABF_ABF_39_CFG_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_ABF_ABF_40_CFG 0x2308  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_EDGE_SMOOTH_NOISE_SCALAR_GR_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_EDGE_SMOOTH_NOISE_SCALAR_GR_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_EDGE_SMOOTH_NOISE_SCALAR_R_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_EDGE_SMOOTH_NOISE_SCALAR_R_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_40_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_41_CFG 0x230c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_EDGE_SMOOTH_NOISE_SCALAR_GB_MASK 0xfff
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_EDGE_SMOOTH_NOISE_SCALAR_GB_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_EDGE_SMOOTH_NOISE_SCALAR_B_MASK 0xfff0000
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_EDGE_SMOOTH_NOISE_SCALAR_B_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_ABF_ABF_41_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_ABF_ABF_42_CFG 0x2310  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_BLS_THRESH_GR_MASK 0x3fff
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_BLS_THRESH_GR_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_BLS_THRESH_R_MASK 0x3fff0000
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_BLS_THRESH_R_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_ABF_ABF_42_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_ABF_ABF_43_CFG 0x2314  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_BLS_THRESH_GB_MASK 0x3fff
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_BLS_THRESH_GB_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_BLS_THRESH_B_MASK 0x3fff0000
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_BLS_THRESH_B_SHIFT 0x10
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_ABF_ABF_43_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_ABF_ABF_44_CFG 0x2318  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_44_CFG_BLS_OFFSET_MASK 0x3fff
#define BPS_BPS_0_CLC_ABF_ABF_44_CFG_BLS_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_44_CFG_UNUSED0_MASK 0xffffc000
#define BPS_BPS_0_CLC_ABF_ABF_44_CFG_UNUSED0_SHIFT 0xe

#define regBPS_BPS_0_CLC_ABF_ABF_45_CFG 0x231c  /*register offset*/
#define BPS_BPS_0_CLC_ABF_ABF_45_CFG_BLS_SCALE_MASK 0x1ffff
#define BPS_BPS_0_CLC_ABF_ABF_45_CFG_BLS_SCALE_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_ABF_45_CFG_UNUSED0_MASK 0xfffe0000
#define BPS_BPS_0_CLC_ABF_ABF_45_CFG_UNUSED0_SHIFT 0x11

#define regBPS_BPS_0_CLC_ABF_TEST_BUS_CTRL 0x23f8  /*register offset*/
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_ABF_SPARE 0x23fc  /*register offset*/
#define BPS_BPS_0_CLC_ABF_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_ABF_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_ABF_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_ABF_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION 0x2400  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_STATUS 0x2404  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG 0x2460  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG 0x2468  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG 0x246c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG 0x2470  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG 0x2474  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG 0x2478  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG 0x247c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG 0x2480  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG 0x2484  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_TEST_BUS_CTRL 0x2488  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_SPARE 0x25fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION 0x2600  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_HW_STATUS 0x2604  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG 0x2608  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_ADDR_MASK 0xff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_UNUSED0_MASK 0xfff00
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_UNUSED0_SHIFT 0x8
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG 0x260c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_LUT_SEL_MASK 0x3
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA 0x2610  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_1 0x2614  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_2 0x2618  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_3 0x261c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_4 0x2620  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_5 0x2624  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_6 0x2628  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_7 0x262c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_8 0x2630  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_9 0x2634  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_10 0x2638  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_11 0x263c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_12 0x2640  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_13 0x2644  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_14 0x2648  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_15 0x264c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD 0x2650  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_STATUS 0x2654  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG 0x2658  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG 0x265c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG 0x2660  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED0_MASK 0xffe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_NUM_SUBBLOCKS_MASK 0x3000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_NUM_SUBBLOCKS_SHIFT 0xc
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_BLOCK_X_MASK 0xf0000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_BLOCK_X_SHIFT 0x10
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_BLOCK_Y_MASK 0xf00000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_BLOCK_Y_SHIFT 0x14
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_SUBBLOCK_X_MASK 0x7000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_SUBBLOCK_X_SHIFT 0x18
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED2_MASK 0x8000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED2_SHIFT 0x1b
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_SUBBLOCK_Y_MASK 0x70000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_INIT_SUBBLOCK_Y_SHIFT 0x1c
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED3_MASK 0x80000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG_UNUSED3_SHIFT 0x1f

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG 0x2668  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG_NUM_BLOCKS_X_MASK 0xf
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG_NUM_BLOCKS_X_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG_NUM_BLOCKS_Y_MASK 0xf0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG_NUM_BLOCKS_Y_SHIFT 0x4
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG_UNUSED0_MASK 0xffffff00
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG_UNUSED0_SHIFT 0x8

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG 0x266c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_BLOCK_WIDTH_MASK 0x7ff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_BLOCK_WIDTH_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_BLOCK_HEIGHT_MASK 0x3ff0000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_BLOCK_HEIGHT_SHIFT 0x10
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG 0x2670  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_SUBBLOCK_WIDTH_MASK 0x7ff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_SUBBLOCK_WIDTH_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_UNUSED0_MASK 0x800
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_INV_SUBBLOCK_WIDTH_MASK 0x1ffff000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_INV_SUBBLOCK_WIDTH_SHIFT 0xc
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG 0x2674  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_SUBBLOCK_HEIGHT_MASK 0x3ff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_SUBBLOCK_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_UNUSED0_MASK 0xc00
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_INV_SUBBLOCK_HEIGHT_MASK 0x1ffff000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_INV_SUBBLOCK_HEIGHT_SHIFT 0xc
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG 0x2678  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_INIT_PIXEL_X_MASK 0x7ff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_INIT_PIXEL_X_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_INIT_PIXEL_Y_MASK 0x3ff0000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_INIT_PIXEL_Y_SHIFT 0x10
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_5_CFG 0x267c  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_5_CFG_PIXEL_OFFSET_MASK 0xfff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_5_CFG_PIXEL_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_5_CFG_UNUSED0_MASK 0xfffff000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_5_CFG_UNUSED0_SHIFT 0xc

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_6_CFG 0x2680  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_6_CFG_INIT_YDELTA_MASK 0xfffff
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_6_CFG_INIT_YDELTA_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_6_CFG_UNUSED0_MASK 0xfff00000
#define BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_6_CFG_UNUSED0_SHIFT 0x14

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL 0x27f8  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_LENS_ROLLOFF_SPARE 0x27fc  /*register offset*/
#define BPS_BPS_0_CLC_LENS_ROLLOFF_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_LENS_ROLLOFF_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_LENS_ROLLOFF_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_LENS_ROLLOFF_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DEMOSAIC_HW_VERSION 0x2800  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DEMOSAIC_HW_STATUS 0x2804  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DEMOSAIC_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DEMOSAIC_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG 0x2860  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_UNUSED0_MASK 0x3fc
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_COSITED_RGB_EN_MASK 0x400
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_COSITED_RGB_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_UNUSED1_MASK 0x800
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_UNUSED1_SHIFT 0xb
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DIR_G_INTERP_DIS_MASK 0x1000
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DIR_G_INTERP_DIS_SHIFT 0xc
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DIR_RB_INTERP_DIS_MASK 0x2000
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DIR_RB_INTERP_DIS_SHIFT 0xd
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DYN_G_CLAMP_EN_MASK 0x4000
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DYN_G_CLAMP_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DYN_RB_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_DYN_RB_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_UNUSED2_MASK 0xffff0000
#define BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG_UNUSED2_SHIFT 0x10

#define regBPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0 0x2868  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_G_GAIN_MASK 0x7fff
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_G_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_B_GAIN_MASK 0x7fff0000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_B_GAIN_SHIFT 0x10
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_1 0x286c  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_1_R_GAIN_MASK 0x7fff
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_1_R_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_1_UNUSED0_MASK 0xffff8000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_1_UNUSED0_SHIFT 0xf

#define regBPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0 0x2870  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_G_OFFSET_MASK 0x7fff
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_G_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_UNUSED0_MASK 0x8000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_UNUSED0_SHIFT 0xf
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_B_OFFSET_MASK 0x7fff0000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_B_OFFSET_SHIFT 0x10
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_UNUSED1_MASK 0x80000000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0_UNUSED1_SHIFT 0x1f

#define regBPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_1 0x2874  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_1_R_OFFSET_MASK 0x7fff
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_1_R_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_1_UNUSED0_MASK 0xffff8000
#define BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_1_UNUSED0_SHIFT 0xf

#define regBPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG 0x2878  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_LAMDA_G_MASK 0xff
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_LAMDA_G_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_UNUSED0_MASK 0xff00
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_UNUSED0_SHIFT 0x8
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_LAMDA_RB_MASK 0xff0000
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_LAMDA_RB_SHIFT 0x10
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_UNUSED1_MASK 0xff000000
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG_UNUSED1_SHIFT 0x18

#define regBPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG 0x287c  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_W_K_MASK 0x3ff
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_W_K_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_A_K_MASK 0xfff0000
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_A_K_SHIFT 0x10
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL 0x29f8  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_DEMOSAIC_SPARE 0x29fc  /*register offset*/
#define BPS_BPS_0_CLC_DEMOSAIC_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DEMOSAIC_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DEMOSAIC_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DEMOSAIC_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_STATS_BG_HW_VERSION 0x2a00  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_STATS_BG_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_STATS_BG_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_STATS_BG_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_STATS_BG_HW_STATUS 0x2a04  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_OVERFLOW_ERROR_MASK 0x2
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_OVERFLOW_ERROR_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_OVERWRITE_MASK 0x4
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_OVERWRITE_SHIFT 0x2
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_STATS_BG_HW_STATUS_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_STATS_BG_MODULE_CFG 0x2a60  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_SAT_STATS_EN_MASK 0x100
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_SAT_STATS_EN_SHIFT 0x8
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_QUAD_SYNC_EN_MASK 0x200
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_QUAD_SYNC_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_SHIFT_BITS_MASK 0x1c00
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_SHIFT_BITS_SHIFT 0xa
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_UNUSED1_MASK 0xe000
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_UNUSED1_SHIFT 0xd
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_RGN_SAMPLE_PATTERN_MASK 0xffff0000
#define BPS_BPS_0_CLC_STATS_BG_MODULE_CFG_RGN_SAMPLE_PATTERN_SHIFT 0x10

#define regBPS_BPS_0_CLC_STATS_BG_CH_Y_CFG 0x2a68  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_Y_STATS_EN_MASK 0x1
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_Y_STATS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_G_SEL_MASK 0x6
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_G_SEL_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_COEF_A0_MASK 0xff0
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_COEF_A0_SHIFT 0x4
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED1_MASK 0x1000
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED1_SHIFT 0xc
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_COEF_A1_MASK 0x1fe000
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_COEF_A1_SHIFT 0xd
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED2_MASK 0x200000
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED2_SHIFT 0x15
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_COEF_A2_MASK 0x3fc00000
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_COEF_A2_SHIFT 0x16
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED3_MASK 0xc0000000
#define BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG_UNUSED3_SHIFT 0x1e

#define regBPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0 0x2a6c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_RGN_H_OFFSET_MASK 0x1fff
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_RGN_H_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_RGN_H_NUM_MASK 0x7f0000
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_RGN_H_NUM_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_1 0x2a70  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_1_RGN_WIDTH_MASK 0x1ff
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_1_RGN_WIDTH_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_1_UNUSED0_MASK 0xfffffe00
#define BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_1_UNUSED0_SHIFT 0x9

#define regBPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0 0x2a74  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_RGN_V_OFFSET_MASK 0x3fff
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_RGN_V_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_RGN_V_NUM_MASK 0x7f0000
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_RGN_V_NUM_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_1 0x2a78  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_1_RGN_HEIGHT_MASK 0x1ff
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_1_RGN_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_1_UNUSED0_MASK 0xfffffe00
#define BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_1_UNUSED0_SHIFT 0x9

#define regBPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG 0x2a7c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_FIRST_RGN_WIDTH_MASK 0x1ff
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_FIRST_RGN_WIDTH_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_UNUSED0_MASK 0xfe00
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_LAST_RGN_WIDTH_MASK 0x1ff0000
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_LAST_RGN_WIDTH_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_UNUSED1_MASK 0xfe000000
#define BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG_UNUSED1_SHIFT 0x19

#define regBPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0 0x2a80  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_R_MAX_MASK 0x3fff
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_R_MAX_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_GR_MAX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_GR_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1 0x2a84  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_B_MAX_MASK 0x3fff
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_B_MAX_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_GB_MAX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_GB_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0 0x2a88  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_R_MIN_MASK 0x3fff
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_R_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_GR_MIN_MASK 0x3fff0000
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_GR_MIN_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1 0x2a8c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_B_MIN_MASK 0x3fff
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_B_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_GB_MIN_MASK 0x3fff0000
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_GB_MIN_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL 0x2bf8  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_STATS_BG_SPARE 0x2bfc  /*register offset*/
#define BPS_BPS_0_CLC_STATS_BG_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_STATS_BG_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_BG_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_STATS_BG_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION 0x2c00  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS 0x2c04  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS_OVERWRITE_MASK 0x2
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS_OVERWRITE_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG 0x2c08  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_ADDR_MASK 0xff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_UNUSED0_MASK 0xfff00
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_UNUSED0_SHIFT 0x8
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG 0x2c0c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_MASK 0x3
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA 0x2c10  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_1 0x2c14  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_2 0x2c18  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_3 0x2c1c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_4 0x2c20  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_5 0x2c24  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_6 0x2c28  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_7 0x2c2c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_8 0x2c30  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_9 0x2c34  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_10 0x2c38  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_11 0x2c3c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_12 0x2c40  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_13 0x2c44  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_14 0x2c48  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_15 0x2c4c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD 0x2c50  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_STATUS 0x2c54  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG 0x2c58  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG 0x2c5c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG 0x2c60  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_HDR_BHIST_CHAN_SEL_MASK 0x100
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_HDR_BHIST_CHAN_SEL_SHIFT 0x8
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_HDR_BHIST_FIELD_SEL_MASK 0x600
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_HDR_BHIST_FIELD_SEL_SHIFT 0x9
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_HDR_BHIST_SITE_SEL_MASK 0x800
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_HDR_BHIST_SITE_SEL_SHIFT 0xb
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_UNUSED1_MASK 0xfffff000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG_UNUSED1_SHIFT 0xc

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG 0x2c68  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_RGN_H_OFFSET_MASK 0x1fff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_RGN_H_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_RGN_V_OFFSET_MASK 0x3fff0000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_RGN_V_OFFSET_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG 0x2c6c  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_RGN_H_NUM_MASK 0xfff
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_RGN_H_NUM_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_RGN_V_NUM_MASK 0x1fff0000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_RGN_V_NUM_SHIFT 0x10
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL 0x2df8  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_STATS_HDR_BHIST_SPARE 0x2dfc  /*register offset*/
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_STATS_HDR_BHIST_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION 0x2e00  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_COLOR_CORRECT_HW_STATUS 0x2e04  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_COLOR_CORRECT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_COLOR_CORRECT_MODULE_CFG 0x2e60  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_CORRECT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_COLOR_CORRECT_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0 0x2e68  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_MATRIX_A0_MASK 0xfff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_MATRIX_A0_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_MATRIX_A1_MASK 0xfff0000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_MATRIX_A1_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_1 0x2e6c  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_1_MATRIX_A2_MASK 0xfff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_1_MATRIX_A2_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_1_UNUSED0_MASK 0xfffff000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_1_UNUSED0_SHIFT 0xc

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0 0x2e70  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_MATRIX_B0_MASK 0xfff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_MATRIX_B0_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_MATRIX_B1_MASK 0xfff0000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_MATRIX_B1_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_1 0x2e74  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_1_MATRIX_B2_MASK 0xfff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_1_MATRIX_B2_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_1_UNUSED0_MASK 0xfffff000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_1_UNUSED0_SHIFT 0xc

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0 0x2e78  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_MATRIX_C0_MASK 0xfff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_MATRIX_C0_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_UNUSED0_MASK 0xf000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_UNUSED0_SHIFT 0xc
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_MATRIX_C1_MASK 0xfff0000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_MATRIX_C1_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_UNUSED1_MASK 0xf0000000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0_UNUSED1_SHIFT 0x1c

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_1 0x2e7c  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_1_MATRIX_C2_MASK 0xfff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_1_MATRIX_C2_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_1_UNUSED0_MASK 0xfffff000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_1_UNUSED0_SHIFT 0xc

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0 0x2e80  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_OFFSET_K0_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_OFFSET_K0_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_OFFSET_K1_MASK 0x1fff0000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_OFFSET_K1_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_1 0x2e84  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_1_OFFSET_K2_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_1_OFFSET_K2_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_1_UNUSED0_MASK 0xffffe000
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_1_UNUSED0_SHIFT 0xd

#define regBPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_SHIFT_M_CFG 0x2e88  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_SHIFT_M_CFG_M_PARAM_MASK 0x3
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_SHIFT_M_CFG_M_PARAM_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_SHIFT_M_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_SHIFT_M_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL 0x2ff8  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_COLOR_CORRECT_SPARE 0x2ffc  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_CORRECT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_CORRECT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_CORRECT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_COLOR_CORRECT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_HW_VERSION 0x3000  /*register offset*/
#define BPS_BPS_0_CLC_GTM_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_GTM_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_GTM_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_GTM_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_GTM_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_GTM_HW_STATUS 0x3004  /*register offset*/
#define BPS_BPS_0_CLC_GTM_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_GTM_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_DMI_CFG 0x3008  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_CFG_ADDR_MASK 0x3f
#define BPS_BPS_0_CLC_GTM_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_DMI_CFG_UNUSED0_MASK 0xfffc0
#define BPS_BPS_0_CLC_GTM_DMI_CFG_UNUSED0_SHIFT 0x6
#define BPS_BPS_0_CLC_GTM_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_GTM_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_GTM_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_GTM_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_GTM_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_GTM_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_GTM_DMI_LUT_CFG 0x300c  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_LUT_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_DMI_DATA 0x3010  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_1 0x3014  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_2 0x3018  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_3 0x301c  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_4 0x3020  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_5 0x3024  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_6 0x3028  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_7 0x302c  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_8 0x3030  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_9 0x3034  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_10 0x3038  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_11 0x303c  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_12 0x3040  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_13 0x3044  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_14 0x3048  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_DATA_15 0x304c  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GTM_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GTM_DMI_CMD 0x3050  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_GTM_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_GTM_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_GTM_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_GTM_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_GTM_DMI_STATUS 0x3054  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_GTM_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG 0x3058  /*register offset*/
#define BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG 0x305c  /*register offset*/
#define BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_MODULE_CFG 0x3060  /*register offset*/
#define BPS_BPS_0_CLC_GTM_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_GTM_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GTM_TEST_BUS_CTRL 0x31f8  /*register offset*/
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_GTM_SPARE 0x31fc  /*register offset*/
#define BPS_BPS_0_CLC_GTM_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_GTM_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_GTM_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GTM_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GLUT_HW_VERSION 0x3200  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_GLUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_GLUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_GLUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_GLUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_GLUT_HW_STATUS 0x3204  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GLUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GLUT_DMI_CFG 0x3208  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_ADDR_MASK 0x3f
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_UNUSED0_MASK 0xfffc0
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_UNUSED0_SHIFT 0x6
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_GLUT_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_GLUT_DMI_LUT_CFG 0x320c  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_MASK 0x3
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA 0x3210  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_1 0x3214  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_2 0x3218  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_3 0x321c  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_4 0x3220  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_5 0x3224  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_6 0x3228  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_7 0x322c  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_8 0x3230  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_9 0x3234  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_10 0x3238  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_11 0x323c  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_12 0x3240  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_13 0x3244  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_14 0x3248  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_DATA_15 0x324c  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_GLUT_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_GLUT_DMI_CMD 0x3250  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_GLUT_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_GLUT_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_GLUT_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_GLUT_DMI_STATUS 0x3254  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GLUT_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG 0x3258  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG 0x325c  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GLUT_MODULE_CFG 0x3260  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GLUT_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL 0x33f8  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_GLUT_SPARE 0x33fc  /*register offset*/
#define BPS_BPS_0_CLC_GLUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_GLUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_GLUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_GLUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION 0x3400  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_COLOR_XFORM_HW_STATUS 0x3404  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_COLOR_XFORM_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_COLOR_XFORM_MODULE_CFG 0x3460  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_XFORM_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_COLOR_XFORM_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0 0x3468  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_MATRIX_M00_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_MATRIX_M00_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_MATRIX_M01_MASK 0x1fff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_MATRIX_M01_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_1 0x346c  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_1_MATRIX_M02_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_1_MATRIX_M02_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_1_UNUSED0_MASK 0xffffe000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_1_UNUSED0_SHIFT 0xd

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG 0x3470  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_OFFSET_S0_MASK 0x7ff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_OFFSET_S0_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_OFFSET_O0_MASK 0x7ff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_OFFSET_O0_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG 0x3474  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0 0x3478  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_MATRIX_M10_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_MATRIX_M10_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_MATRIX_M11_MASK 0x1fff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_MATRIX_M11_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_1 0x347c  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_1_MATRIX_M12_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_1_MATRIX_M12_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_1_UNUSED0_MASK 0xffffe000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_1_UNUSED0_SHIFT 0xd

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG 0x3480  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_OFFSET_S1_MASK 0x7ff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_OFFSET_S1_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_OFFSET_O1_MASK 0x7ff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_OFFSET_O1_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG 0x3484  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0 0x3488  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_MATRIX_M20_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_MATRIX_M20_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_UNUSED0_MASK 0xe000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_MATRIX_M21_MASK 0x1fff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_MATRIX_M21_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_UNUSED1_MASK 0xe0000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0_UNUSED1_SHIFT 0x1d

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_1 0x348c  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_1_MATRIX_M22_MASK 0x1fff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_1_MATRIX_M22_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_1_UNUSED0_MASK 0xffffe000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_1_UNUSED0_SHIFT 0xd

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG 0x3490  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_OFFSET_S2_MASK 0x7ff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_OFFSET_S2_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_UNUSED0_MASK 0xf800
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_UNUSED0_SHIFT 0xb
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_OFFSET_O2_MASK 0x7ff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_OFFSET_O2_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG 0x3494  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_COLOR_XFORM_SPARE 0x35fc  /*register offset*/
#define BPS_BPS_0_CLC_COLOR_XFORM_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_COLOR_XFORM_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_COLOR_XFORM_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_COLOR_XFORM_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION 0x3600  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_STATUS 0x3604  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG 0x3660  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG 0x3668  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG 0x366c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG 0x3670  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG 0x3674  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG 0x3678  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG 0x367c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG 0x3680  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG 0x3684  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_TEST_BUS_CTRL 0x3688  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_SPARE 0x37fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION 0x3800  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_STATUS 0x3804  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG 0x3860  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG 0x3868  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG 0x386c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG 0x3870  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG 0x3874  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG 0x3878  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG 0x387c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG 0x3880  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG 0x3884  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_TEST_BUS_CTRL 0x3888  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_SPARE 0x39fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION 0x3a00  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS 0x3a04  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_OVERFLOW_ERROR_MASK 0x2
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_OVERFLOW_ERROR_SHIFT 0x1
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_OVERWRITE_MASK 0x4
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_OVERWRITE_SHIFT 0x2
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_MODULE_CFG 0x3a60  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG 0x3a64  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED0_MASK 0x1ff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED0_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_HORIZONTAL_SCALE_EN_MASK 0x200
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_HORIZONTAL_SCALE_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_VERTICAL_SCALE_EN_MASK 0x400
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_VERTICAL_SCALE_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED1_MASK 0x800
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED1_SHIFT 0xb
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_HORIZONTAL_ROUNDING_MASK 0x3000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_HORIZONTAL_ROUNDING_SHIFT 0xc
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED2_MASK 0x4000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED2_SHIFT 0xe
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_VERTICAL_ROUNDING_MASK 0x18000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_VERTICAL_ROUNDING_SHIFT 0xf
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED3_MASK 0x20000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED3_SHIFT 0x11
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_HORIZONTAL_TERMINATION_EN_MASK 0x40000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_HORIZONTAL_TERMINATION_EN_SHIFT 0x12
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_VERTICAL_TERMINATION_EN_MASK 0x80000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_VERTICAL_TERMINATION_EN_SHIFT 0x13
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED4_MASK 0xfff00000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG_UNUSED4_SHIFT 0x14

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG 0x3a68  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_HEIGHT_MASK 0x3fff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_WIDTH_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_WIDTH_SHIFT 0x10
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG 0x3a6c  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG_PHASE_STEP_H_MASK 0x1fffffff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG_PHASE_STEP_H_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG_UNUSED0_MASK 0x20000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG_UNUSED0_SHIFT 0x1d
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG_H_INTERP_RESO_MASK 0xc0000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG_H_INTERP_RESO_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_PHASE_CFG 0x3a70  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_PHASE_CFG_PHASE_INIT_H_MASK 0x1fffffff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_PHASE_CFG_PHASE_INIT_H_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_PHASE_CFG_UNUSED0_MASK 0xe0000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_PHASE_CFG_UNUSED0_SHIFT 0x1d

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG 0x3a74  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG_PHASE_STEP_V_MASK 0x1fffffff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG_PHASE_STEP_V_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG_UNUSED0_MASK 0x20000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG_UNUSED0_SHIFT 0x1d
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG_V_INTERP_RESO_MASK 0xc0000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG_V_INTERP_RESO_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_PHASE_CFG 0x3a78  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_PHASE_CFG_PHASE_INIT_V_MASK 0x1fffffff
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_PHASE_CFG_PHASE_INIT_V_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_PHASE_CFG_UNUSED0_MASK 0xe0000000
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_PHASE_CFG_UNUSED0_SHIFT 0x1d

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_TEST_BUS_CTRL 0x3bf8  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CHROMA_SUBSAMPLE_SPARE 0x3bfc  /*register offset*/
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HNR_HW_VERSION 0x3c00  /*register offset*/
#define BPS_BPS_0_CLC_HNR_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_HNR_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_HW_STATUS 0x3c04  /*register offset*/
#define BPS_BPS_0_CLC_HNR_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_HNR_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HNR_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HNR_DMI_CFG 0x3c08  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_CFG_ADDR_MASK 0x1ff
#define BPS_BPS_0_CLC_HNR_DMI_CFG_ADDR_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_DMI_CFG_UNUSED0_MASK 0xffe00
#define BPS_BPS_0_CLC_HNR_DMI_CFG_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_HNR_DMI_CFG_AUTO_LOAD_EN_MASK 0x100000
#define BPS_BPS_0_CLC_HNR_DMI_CFG_AUTO_LOAD_EN_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_DMI_CFG_AUTO_LOAD_PATTERN_MASK 0x600000
#define BPS_BPS_0_CLC_HNR_DMI_CFG_AUTO_LOAD_PATTERN_SHIFT 0x15
#define BPS_BPS_0_CLC_HNR_DMI_CFG_UNUSED1_MASK 0xff800000
#define BPS_BPS_0_CLC_HNR_DMI_CFG_UNUSED1_SHIFT 0x17

#define regBPS_BPS_0_CLC_HNR_DMI_LUT_CFG 0x3c0c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_MASK 0x7
#define BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_HNR_DMI_DATA 0x3c10  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_1 0x3c14  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_1_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_1_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_2 0x3c18  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_2_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_2_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_3 0x3c1c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_3_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_3_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_4 0x3c20  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_4_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_4_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_5 0x3c24  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_5_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_5_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_6 0x3c28  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_6_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_6_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_7 0x3c2c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_7_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_7_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_8 0x3c30  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_8_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_8_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_9 0x3c34  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_9_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_9_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_10 0x3c38  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_10_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_10_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_11 0x3c3c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_11_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_11_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_12 0x3c40  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_12_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_12_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_13 0x3c44  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_13_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_13_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_14 0x3c48  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_14_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_14_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_DATA_15 0x3c4c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_DATA_15_DATA_MASK 0xffffffff
#define BPS_BPS_0_CLC_HNR_DMI_DATA_15_DATA_SHIFT 0x0

#define regBPS_BPS_0_CLC_HNR_DMI_CMD 0x3c50  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_CMD_AUTO_LOAD_CMD_MASK 0x1
#define BPS_BPS_0_CLC_HNR_DMI_CMD_AUTO_LOAD_CMD_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_DMI_CMD_AUTO_LOAD_STATUS_CLR_MASK 0x2
#define BPS_BPS_0_CLC_HNR_DMI_CMD_AUTO_LOAD_STATUS_CLR_SHIFT 0x1
#define BPS_BPS_0_CLC_HNR_DMI_CMD_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_CLC_HNR_DMI_CMD_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_CLC_HNR_DMI_STATUS 0x3c54  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_STATUS_AUTO_LOAD_DONE_MASK 0x1
#define BPS_BPS_0_CLC_HNR_DMI_STATUS_AUTO_LOAD_DONE_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_DMI_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HNR_DMI_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG 0x3c58  /*register offset*/
#define BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG 0x3c5c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_BANK_SEL_MASK 0x1
#define BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_BANK_SEL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_HNR_MODULE_CFG 0x3c60  /*register offset*/
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_STRIPE_AUTO_CROP_DIS_MASK 0x2
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_STRIPE_AUTO_CROP_DIS_SHIFT 0x1
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_UNUSED0_MASK 0xfc
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_BLEND_SNR_EN_MASK 0x100
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_BLEND_SNR_EN_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_BLEND_CNR_EN_MASK 0x200
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_BLEND_CNR_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_BLEND_ENABLE_MASK 0x400
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_BLEND_ENABLE_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_LPF3_EN_MASK 0x800
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_LPF3_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_FNR_EN_MASK 0x1000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_FNR_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_FD_SNR_EN_MASK 0x2000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_FD_SNR_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_SNR_EN_MASK 0x4000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_SNR_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_CNR_EN_MASK 0x8000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_CNR_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_RNR_EN_MASK 0x10000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_RNR_EN_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_LNR_EN_MASK 0x20000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_LNR_EN_SHIFT 0x11
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_UNUSED1_MASK 0xfffc0000
#define BPS_BPS_0_CLC_HNR_MODULE_CFG_UNUSED1_SHIFT 0x12

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0 0x3c68  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_0_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_0_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_1_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_1_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_2_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_2_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_3_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0_FILTERING_NR_GAIN_ARR_3_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1 0x3c6c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_4_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_4_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_5_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_5_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_6_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_6_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_7_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1_FILTERING_NR_GAIN_ARR_7_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2 0x3c70  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_8_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_8_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_9_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_9_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_10_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_10_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_11_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2_FILTERING_NR_GAIN_ARR_11_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3 0x3c74  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_12_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_12_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_13_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_13_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_14_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_14_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_15_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3_FILTERING_NR_GAIN_ARR_15_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4 0x3c78  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_16_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_16_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_17_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_17_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_18_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_18_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_19_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4_FILTERING_NR_GAIN_ARR_19_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5 0x3c7c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_20_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_20_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_21_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_21_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_22_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_22_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_23_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5_FILTERING_NR_GAIN_ARR_23_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6 0x3c80  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_24_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_24_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_25_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_25_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_26_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_26_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_27_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6_FILTERING_NR_GAIN_ARR_27_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7 0x3c84  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_28_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_28_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_29_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_29_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_30_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_30_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_31_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7_FILTERING_NR_GAIN_ARR_31_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_8 0x3c88  /*register offset*/
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_8_FILTERING_NR_GAIN_ARR_32_MASK 0xff
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_8_FILTERING_NR_GAIN_ARR_32_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_8_UNUSED0_MASK 0xffffff00
#define BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_8_UNUSED0_SHIFT 0x8

#define regBPS_BPS_0_CLC_HNR_CNR_CFG_0 0x3c8c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_THRD_GAP_V_MASK 0x7
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_THRD_GAP_V_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_UNUSED0_MASK 0x8
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_LOW_THRD_V_MASK 0xff0
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_LOW_THRD_V_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_THRD_GAP_U_MASK 0x7000
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_THRD_GAP_U_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_UNUSED1_MASK 0x8000
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_UNUSED1_SHIFT 0xf
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_LOW_THRD_U_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_CNR_LOW_THRD_U_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_UNUSED2_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_CNR_CFG_0_UNUSED2_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_CNR_CFG_1 0x3c90  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_CFG_1_CNR_SCALE_MASK 0xf
#define BPS_BPS_0_CLC_HNR_CNR_CFG_1_CNR_SCALE_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_CFG_1_CNR_ADJ_GAIN_MASK 0x3f0
#define BPS_BPS_0_CLC_HNR_CNR_CFG_1_CNR_ADJ_GAIN_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_CNR_CFG_1_UNUSED0_MASK 0xfffffc00
#define BPS_BPS_0_CLC_HNR_CNR_CFG_1_UNUSED0_SHIFT 0xa

#define regBPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0 0x3c94  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_0_MASK 0x3f
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_0_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_1_MASK 0xfc0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_1_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_2_MASK 0x3f000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_2_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_3_MASK 0xfc0000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_3_SHIFT 0x12
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_4_MASK 0x3f000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_CNR_GAIN_ARR_4_SHIFT 0x18
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1 0x3c98  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_5_MASK 0x3f
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_5_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_6_MASK 0xfc0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_6_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_7_MASK 0x3f000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_7_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_8_MASK 0xfc0000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_8_SHIFT 0x12
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_9_MASK 0x3f000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_CNR_GAIN_ARR_9_SHIFT 0x18
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2 0x3c9c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_10_MASK 0x3f
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_10_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_11_MASK 0xfc0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_11_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_12_MASK 0x3f000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_12_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_13_MASK 0xfc0000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_13_SHIFT 0x12
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_14_MASK 0x3f000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_CNR_GAIN_ARR_14_SHIFT 0x18
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3 0x3ca0  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_15_MASK 0x3f
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_15_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_16_MASK 0xfc0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_16_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_17_MASK 0x3f000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_17_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_18_MASK 0xfc0000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_18_SHIFT 0x12
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_19_MASK 0x3f000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_CNR_GAIN_ARR_19_SHIFT 0x18
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4 0x3ca4  /*register offset*/
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_20_MASK 0x3f
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_20_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_21_MASK 0xfc0
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_21_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_22_MASK 0x3f000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_22_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_23_MASK 0xfc0000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_23_SHIFT 0x12
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_24_MASK 0x3f000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_CNR_GAIN_ARR_24_SHIFT 0x18
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_SNR_CFG_0 0x3ca8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_HUE_MAX_MASK 0xff
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_HUE_MAX_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_HUE_MIN_MASK 0x3ff00
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_HUE_MIN_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_UNUSED0_MASK 0xc0000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_UNUSED0_SHIFT 0x12
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_Y_MIN_MASK 0xff00000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_Y_MIN_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_SMOOTHING_STR_MASK 0x30000000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_SNR_SKIN_SMOOTHING_STR_SHIFT 0x1c
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_0_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_SNR_CFG_1 0x3cac  /*register offset*/
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_SKIN_Y_MAX_MASK 0xff
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_SKIN_Y_MAX_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_QSTEP_SKIN_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_QSTEP_SKIN_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_QSTEP_NONSKIN_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_QSTEP_NONSKIN_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_BOUNDARY_PROBABILITY_MASK 0xf000000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_SNR_BOUNDARY_PROBABILITY_SHIFT 0x18
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_UNUSED0_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_1_UNUSED0_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_SNR_CFG_2 0x3cb0  /*register offset*/
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SAT_MAX_SLOPE_MASK 0xff
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SAT_MAX_SLOPE_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SAT_MIN_SLOPE_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SAT_MIN_SLOPE_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SKIN_YMAX_SAT_MAX_MASK 0xff0000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SKIN_YMAX_SAT_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SKIN_YMAX_SAT_MIN_MASK 0xff000000
#define BPS_BPS_0_CLC_HNR_SNR_CFG_2_SNR_SKIN_YMAX_SAT_MIN_SHIFT 0x18

#define regBPS_BPS_0_CLC_HNR_FACE_CFG 0x3cb4  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_CFG_FACE_NUM_MASK 0x7
#define BPS_BPS_0_CLC_HNR_FACE_CFG_FACE_NUM_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_HNR_FACE_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_HNR_FACE_OFFSET_CFG 0x3cb8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_OFFSET_CFG_FACE_HORIZONTAL_OFFSET_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_FACE_OFFSET_CFG_FACE_HORIZONTAL_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_OFFSET_CFG_FACE_VERTICAL_OFFSET_MASK 0xffff0000
#define BPS_BPS_0_CLC_HNR_FACE_OFFSET_CFG_FACE_VERTICAL_OFFSET_SHIFT 0x10

#define regBPS_BPS_0_CLC_HNR_FACE_0_CENTER_CFG 0x3cbc  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_0_CENTER_CFG_FACE_CENTER_HORIZONTAL_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_FACE_0_CENTER_CFG_FACE_CENTER_HORIZONTAL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_0_CENTER_CFG_FACE_CENTER_VERTICAL_MASK 0xffff0000
#define BPS_BPS_0_CLC_HNR_FACE_0_CENTER_CFG_FACE_CENTER_VERTICAL_SHIFT 0x10

#define regBPS_BPS_0_CLC_HNR_FACE_1_CENTER_CFG 0x3cc0  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_1_CENTER_CFG_FACE_CENTER_HORIZONTAL_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_FACE_1_CENTER_CFG_FACE_CENTER_HORIZONTAL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_1_CENTER_CFG_FACE_CENTER_VERTICAL_MASK 0xffff0000
#define BPS_BPS_0_CLC_HNR_FACE_1_CENTER_CFG_FACE_CENTER_VERTICAL_SHIFT 0x10

#define regBPS_BPS_0_CLC_HNR_FACE_2_CENTER_CFG 0x3cc4  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_2_CENTER_CFG_FACE_CENTER_HORIZONTAL_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_FACE_2_CENTER_CFG_FACE_CENTER_HORIZONTAL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_2_CENTER_CFG_FACE_CENTER_VERTICAL_MASK 0xffff0000
#define BPS_BPS_0_CLC_HNR_FACE_2_CENTER_CFG_FACE_CENTER_VERTICAL_SHIFT 0x10

#define regBPS_BPS_0_CLC_HNR_FACE_3_CENTER_CFG 0x3cc8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_3_CENTER_CFG_FACE_CENTER_HORIZONTAL_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_FACE_3_CENTER_CFG_FACE_CENTER_HORIZONTAL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_3_CENTER_CFG_FACE_CENTER_VERTICAL_MASK 0xffff0000
#define BPS_BPS_0_CLC_HNR_FACE_3_CENTER_CFG_FACE_CENTER_VERTICAL_SHIFT 0x10

#define regBPS_BPS_0_CLC_HNR_FACE_4_CENTER_CFG 0x3ccc  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_4_CENTER_CFG_FACE_CENTER_HORIZONTAL_MASK 0xffff
#define BPS_BPS_0_CLC_HNR_FACE_4_CENTER_CFG_FACE_CENTER_HORIZONTAL_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_4_CENTER_CFG_FACE_CENTER_VERTICAL_MASK 0xffff0000
#define BPS_BPS_0_CLC_HNR_FACE_4_CENTER_CFG_FACE_CENTER_VERTICAL_SHIFT 0x10

#define regBPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG 0x3cd0  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_RADIUS_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_RADIUS_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED0_MASK 0x30
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_RADIUS_BOUNDARY_MASK 0x3fc0
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_RADIUS_BOUNDARY_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_SLOPE_SHIFT_MASK 0x70000
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_SLOPE_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED2_MASK 0x80000
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED2_SHIFT 0x13
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_RADIUS_SLOPE_MASK 0xff00000
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_FACE_RADIUS_SLOPE_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED3_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG_UNUSED3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG 0x3cd4  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_RADIUS_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_RADIUS_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED0_MASK 0x30
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_RADIUS_BOUNDARY_MASK 0x3fc0
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_RADIUS_BOUNDARY_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_SLOPE_SHIFT_MASK 0x70000
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_SLOPE_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED2_MASK 0x80000
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED2_SHIFT 0x13
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_RADIUS_SLOPE_MASK 0xff00000
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_FACE_RADIUS_SLOPE_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED3_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG_UNUSED3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG 0x3cd8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_RADIUS_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_RADIUS_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED0_MASK 0x30
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_RADIUS_BOUNDARY_MASK 0x3fc0
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_RADIUS_BOUNDARY_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_SLOPE_SHIFT_MASK 0x70000
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_SLOPE_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED2_MASK 0x80000
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED2_SHIFT 0x13
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_RADIUS_SLOPE_MASK 0xff00000
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_FACE_RADIUS_SLOPE_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED3_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG_UNUSED3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG 0x3cdc  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_RADIUS_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_RADIUS_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED0_MASK 0x30
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_RADIUS_BOUNDARY_MASK 0x3fc0
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_RADIUS_BOUNDARY_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_SLOPE_SHIFT_MASK 0x70000
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_SLOPE_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED2_MASK 0x80000
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED2_SHIFT 0x13
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_RADIUS_SLOPE_MASK 0xff00000
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_FACE_RADIUS_SLOPE_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED3_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG_UNUSED3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG 0x3ce0  /*register offset*/
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_RADIUS_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_RADIUS_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED0_MASK 0x30
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_RADIUS_BOUNDARY_MASK 0x3fc0
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_RADIUS_BOUNDARY_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED1_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED1_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_SLOPE_SHIFT_MASK 0x70000
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_SLOPE_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED2_MASK 0x80000
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED2_SHIFT 0x13
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_RADIUS_SLOPE_MASK 0xff00000
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_FACE_RADIUS_SLOPE_SHIFT 0x14
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED3_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG_UNUSED3_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0 0x3ce4  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_RNR_BASE_0_MASK 0x3ff
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_RNR_BASE_0_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_RNR_ANCHOR_0_MASK 0x3ff0000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_RNR_ANCHOR_0_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1 0x3ce8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_RNR_BASE_1_MASK 0x3ff
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_RNR_BASE_1_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_RNR_ANCHOR_1_MASK 0x3ff0000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_RNR_ANCHOR_1_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2 0x3cec  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_RNR_BASE_2_MASK 0x3ff
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_RNR_BASE_2_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_RNR_ANCHOR_2_MASK 0x3ff0000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_RNR_ANCHOR_2_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3 0x3cf0  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_RNR_BASE_3_MASK 0x3ff
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_RNR_BASE_3_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_RNR_ANCHOR_3_MASK 0x3ff0000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_RNR_ANCHOR_3_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4 0x3cf4  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_RNR_BASE_4_MASK 0x3ff
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_RNR_BASE_4_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_RNR_ANCHOR_4_MASK 0x3ff0000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_RNR_ANCHOR_4_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5 0x3cf8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_RNR_BASE_5_MASK 0x3ff
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_RNR_BASE_5_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_RNR_ANCHOR_5_MASK 0x3ff0000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_RNR_ANCHOR_5_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0 0x3cfc  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_RNR_SHIFT_0_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_RNR_SHIFT_0_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_RNR_SLOPE_0_MASK 0x7ff0000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_RNR_SLOPE_0_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1 0x3d00  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_RNR_SHIFT_1_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_RNR_SHIFT_1_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_RNR_SLOPE_1_MASK 0x7ff0000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_RNR_SLOPE_1_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2 0x3d04  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_RNR_SHIFT_2_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_RNR_SHIFT_2_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_RNR_SLOPE_2_MASK 0x7ff0000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_RNR_SLOPE_2_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3 0x3d08  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_RNR_SHIFT_3_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_RNR_SHIFT_3_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_RNR_SLOPE_3_MASK 0x7ff0000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_RNR_SLOPE_3_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4 0x3d0c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_RNR_SHIFT_4_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_RNR_SHIFT_4_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_RNR_SLOPE_4_MASK 0x7ff0000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_RNR_SLOPE_4_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5 0x3d10  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_RNR_SHIFT_5_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_RNR_SHIFT_5_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_UNUSED0_MASK 0xfff0
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_RNR_SLOPE_5_MASK 0x7ff0000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_RNR_SLOPE_5_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_UNUSED1_MASK 0xf8000000
#define BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5_UNUSED1_SHIFT 0x1b

#define regBPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET 0x3d14  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_RNR_BY_MASK 0x3fff
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_RNR_BY_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_RNR_BX_MASK 0x3fff0000
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_RNR_BX_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_HNR_RNR_R_SQUARE_INIT 0x3d18  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_R_SQUARE_INIT_RNR_R_SQUARE_INIT_MASK 0xfffffff
#define BPS_BPS_0_CLC_HNR_RNR_R_SQUARE_INIT_RNR_R_SQUARE_INIT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_R_SQUARE_INIT_UNUSED0_MASK 0xf0000000
#define BPS_BPS_0_CLC_HNR_RNR_R_SQUARE_INIT_UNUSED0_SHIFT 0x1c

#define regBPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT 0x3d1c  /*register offset*/
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_RNR_R_SQUARE_SHIFT_MASK 0xf
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_RNR_R_SQUARE_SHIFT_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_UNUSED0_MASK 0xf0
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_RNR_R_SQUARE_SCALE_MASK 0x7f00
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_RNR_R_SQUARE_SCALE_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_UNUSED1_MASK 0xffff8000
#define BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT_UNUSED1_SHIFT 0xf

#define regBPS_BPS_0_CLC_HNR_LPF3_CFG 0x3d20  /*register offset*/
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_LPF3_OFFSET_MASK 0xff
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_LPF3_OFFSET_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_LPF3_PERCENT_MASK 0xff00
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_LPF3_PERCENT_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_LPF3_STRENGTH_MASK 0x70000
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_LPF3_STRENGTH_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_UNUSED0_MASK 0xfff80000
#define BPS_BPS_0_CLC_HNR_LPF3_CFG_UNUSED0_SHIFT 0x13

#define regBPS_BPS_0_CLC_HNR_MISC_CFG 0x3d24  /*register offset*/
#define BPS_BPS_0_CLC_HNR_MISC_CFG_BLEND_CNR_ADJ_GAIN_MASK 0x3f
#define BPS_BPS_0_CLC_HNR_MISC_CFG_BLEND_CNR_ADJ_GAIN_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED0_MASK 0xc0
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED0_SHIFT 0x6
#define BPS_BPS_0_CLC_HNR_MISC_CFG_ABS_AMP_SHIFT_MASK 0x300
#define BPS_BPS_0_CLC_HNR_MISC_CFG_ABS_AMP_SHIFT_SHIFT 0x8
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED1_MASK 0xc00
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED1_SHIFT 0xa
#define BPS_BPS_0_CLC_HNR_MISC_CFG_FNR_AC_SHIFT_MASK 0x3000
#define BPS_BPS_0_CLC_HNR_MISC_CFG_FNR_AC_SHIFT_SHIFT 0xc
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED2_MASK 0xc000
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED2_SHIFT 0xe
#define BPS_BPS_0_CLC_HNR_MISC_CFG_LNR_SHIFT_MASK 0x30000
#define BPS_BPS_0_CLC_HNR_MISC_CFG_LNR_SHIFT_SHIFT 0x10
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED3_MASK 0xfffc0000
#define BPS_BPS_0_CLC_HNR_MISC_CFG_UNUSED3_SHIFT 0x12

#define regBPS_BPS_0_CLC_HNR_TEST_BUS_CTRL 0x3df8  /*register offset*/
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_HNR_SPARE 0x3dfc  /*register offset*/
#define BPS_BPS_0_CLC_HNR_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_HNR_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_HNR_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_HNR_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION 0x3e00  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS 0x3e04  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG 0x3e60  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG 0x3e68  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG 0x3e6c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG 0x3e70  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG 0x3e74  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG 0x3e78  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG 0x3e7c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG 0x3e80  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG 0x3e84  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL 0x3e88  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_SPARE 0x3ffc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION 0x4000  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS 0x4004  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG 0x4060  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG 0x4068  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG 0x406c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG 0x4070  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG 0x4074  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG 0x4078  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG 0x407c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG 0x4080  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG 0x4084  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL 0x4088  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_SPARE 0x41fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION 0x4200  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_STATUS 0x4204  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG 0x4260  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_FLUSH_PACE_CNT_MASK 0x1f00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_FLUSH_PACE_CNT_SHIFT 0x8
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xe000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0xd
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_HEIGHT_MASK 0x7fff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_HEIGHT_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED2_MASK 0x80000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED2_SHIFT 0x1f

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF 0x4268  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_COEFF_07_MASK 0x1ff
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_COEFF_07_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_UNUSED0_MASK 0x200
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_COEFF_16_MASK 0x7fc00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_COEFF_16_SHIFT 0xa
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_UNUSED1_MASK 0x80000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_UNUSED1_SHIFT 0x13
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_COEFF_25_MASK 0x1ff00000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_COEFF_25_SHIFT 0x14
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_UNUSED2_MASK 0xe0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF_UNUSED2_SHIFT 0x1d

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL 0x43f8  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_SPARE 0x43fc  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION 0x4400  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_STATUS 0x4404  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG 0x4460  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_FLUSH_PACE_CNT_MASK 0x1f00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_FLUSH_PACE_CNT_SHIFT 0x8
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xe000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0xd
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_HEIGHT_MASK 0x3fff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_HEIGHT_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_UNUSED2_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG_UNUSED2_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL 0x45f8  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_SPARE 0x45fc  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION 0x4600  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS 0x4604  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG 0x4660  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG 0x4668  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG 0x466c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG 0x4670  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG 0x4674  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG 0x4678  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG 0x467c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG 0x4680  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG 0x4684  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL 0x4688  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_SPARE 0x47fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION 0x4800  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS 0x4804  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG 0x4860  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG 0x4868  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG 0x486c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG 0x4870  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG 0x4874  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG 0x4878  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG 0x487c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG 0x4880  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG 0x4884  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL 0x4888  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_SPARE 0x49fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION 0x4a00  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_STATUS 0x4a04  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG 0x4a60  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_PACK_MODE_MASK 0x100
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_PACK_MODE_SHIFT 0x8
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_UNUSED1_MASK 0xe00
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_UNUSED1_SHIFT 0x9
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_FLUSH_PACE_CNT_MASK 0x1f000
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_FLUSH_PACE_CNT_SHIFT 0xc
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_UNUSED2_MASK 0xfffe0000
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG_UNUSED2_SHIFT 0x11

#define regBPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL 0x4bf8  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_SPARE 0x4bfc  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION 0x4c00  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_STATUS 0x4c04  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG 0x4c60  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG 0x4c68  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG 0x4c6c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG 0x4c70  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG 0x4c74  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG 0x4c78  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG 0x4c7c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG 0x4c80  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG 0x4c84  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL 0x4c88  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_SPARE 0x4dfc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION 0x4e00  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_STATUS 0x4e04  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG 0x4e60  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG 0x4e68  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG 0x4e6c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG 0x4e70  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG 0x4e74  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG 0x4e78  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG 0x4e7c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG 0x4e80  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG 0x4e84  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL 0x4e88  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_SPARE 0x4ffc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION 0x5000  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_STATUS 0x5004  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG 0x5060  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_FLUSH_PACE_CNT_MASK 0x1f00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_FLUSH_PACE_CNT_SHIFT 0x8
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xe000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0xd
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_HEIGHT_MASK 0x7fff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_HEIGHT_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_UNUSED2_MASK 0x80000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG_UNUSED2_SHIFT 0x1f

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF 0x5068  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_COEFF_07_MASK 0x1ff
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_COEFF_07_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_UNUSED0_MASK 0x200
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_UNUSED0_SHIFT 0x9
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_COEFF_16_MASK 0x7fc00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_COEFF_16_SHIFT 0xa
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_UNUSED1_MASK 0x80000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_UNUSED1_SHIFT 0x13
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_COEFF_25_MASK 0x1ff00000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_COEFF_25_SHIFT 0x14
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_UNUSED2_MASK 0xe0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF_UNUSED2_SHIFT 0x1d

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL 0x51f8  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_SPARE 0x51fc  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION 0x5200  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_STATUS 0x5204  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG 0x5260  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_FLUSH_PACE_CNT_MASK 0x1f00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_FLUSH_PACE_CNT_SHIFT 0x8
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xe000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0xd
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_HEIGHT_MASK 0x3fff0000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_HEIGHT_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_UNUSED2_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG_UNUSED2_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL 0x53f8  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_SPARE 0x53fc  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION 0x5400  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_STATUS 0x5404  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG 0x5460  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG 0x5468  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG 0x546c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG 0x5470  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG 0x5474  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG 0x5478  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG 0x547c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG 0x5480  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG 0x5484  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL 0x5488  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_SPARE 0x55fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION 0x5600  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_STATUS 0x5604  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG 0x5660  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG 0x5668  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG 0x566c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG 0x5670  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG 0x5674  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG 0x5678  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG 0x567c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG 0x5680  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG 0x5684  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL 0x5688  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_SPARE 0x57fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION 0x5800  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_R2PD_DS16_OUT_HW_STATUS 0x5804  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG 0x5860  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_PACK_MODE_MASK 0x100
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_PACK_MODE_SHIFT 0x8
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_UNUSED1_MASK 0xe00
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_UNUSED1_SHIFT 0x9
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_FLUSH_PACE_CNT_MASK 0x1f000
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_FLUSH_PACE_CNT_SHIFT 0xc
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_UNUSED2_MASK 0xfffe0000
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG_UNUSED2_SHIFT 0x11

#define regBPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL 0x59f8  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_EN_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xf0
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_UNUSED1_MASK 0xffffff00
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL_UNUSED1_SHIFT 0x8

#define regBPS_BPS_0_CLC_R2PD_DS16_OUT_SPARE 0x59fc  /*register offset*/
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_R2PD_DS16_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION 0x5a00  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_STATUS 0x5a04  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG 0x5a60  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG 0x5a68  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG 0x5a6c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG 0x5a70  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG 0x5a74  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG 0x5a78  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG 0x5a7c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG 0x5a80  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG 0x5a84  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL 0x5a88  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_SPARE 0x5bfc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION 0x5c00  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_STATUS 0x5c04  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG 0x5c60  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG 0x5c68  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG 0x5c6c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG 0x5c70  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG 0x5c74  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG 0x5c78  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG 0x5c7c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG 0x5c80  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG 0x5c84  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL 0x5c88  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_SPARE 0x5dfc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION 0x5e00  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS 0x5e04  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_OVERFLOW_ERROR_MASK 0x2
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_OVERFLOW_ERROR_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_OVERWRITE_MASK 0x4
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_OVERWRITE_SHIFT 0x2
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_MODULE_CFG 0x5e60  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG 0x5e64  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED0_MASK 0x1ff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED0_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_HORIZONTAL_SCALE_EN_MASK 0x200
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_HORIZONTAL_SCALE_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_VERTICAL_SCALE_EN_MASK 0x400
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_VERTICAL_SCALE_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED1_MASK 0x800
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED1_SHIFT 0xb
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_HORIZONTAL_ROUNDING_MASK 0x3000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_HORIZONTAL_ROUNDING_SHIFT 0xc
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED2_MASK 0x4000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED2_SHIFT 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_VERTICAL_ROUNDING_MASK 0x18000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_VERTICAL_ROUNDING_SHIFT 0xf
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED3_MASK 0x20000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED3_SHIFT 0x11
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_HORIZONTAL_TERMINATION_EN_MASK 0x40000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_HORIZONTAL_TERMINATION_EN_SHIFT 0x12
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_VERTICAL_TERMINATION_EN_MASK 0x80000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_VERTICAL_TERMINATION_EN_SHIFT 0x13
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED4_MASK 0xfff00000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG_UNUSED4_SHIFT 0x14

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG 0x5e68  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_INPUT_HEIGHT_MASK 0x3fff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_INPUT_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_INPUT_WIDTH_MASK 0x3fff0000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_INPUT_WIDTH_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG 0x5e6c  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG_PHASE_STEP_H_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG_PHASE_STEP_H_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG_UNUSED0_MASK 0x20000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG_UNUSED0_SHIFT 0x1d
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG_H_INTERP_RESO_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG_H_INTERP_RESO_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_PHASE_CFG 0x5e70  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_PHASE_CFG_PHASE_INIT_H_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_PHASE_CFG_PHASE_INIT_H_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_PHASE_CFG_UNUSED0_MASK 0xe0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_PHASE_CFG_UNUSED0_SHIFT 0x1d

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG 0x5e74  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG_PHASE_STEP_V_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG_PHASE_STEP_V_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG_UNUSED0_MASK 0x20000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG_UNUSED0_SHIFT 0x1d
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG_V_INTERP_RESO_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG_V_INTERP_RESO_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_PHASE_CFG 0x5e78  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_PHASE_CFG_PHASE_INIT_V_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_PHASE_CFG_PHASE_INIT_V_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_PHASE_CFG_UNUSED0_MASK 0xe0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_PHASE_CFG_UNUSED0_SHIFT 0x1d

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_TEST_BUS_CTRL 0x5ff8  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_SPARE 0x5ffc  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION 0x6000  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS 0x6004  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_OVERFLOW_ERROR_MASK 0x2
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_OVERFLOW_ERROR_SHIFT 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_OVERWRITE_MASK 0x4
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_OVERWRITE_SHIFT 0x2
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_MODULE_CFG 0x6060  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_MODULE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG 0x6064  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED0_MASK 0x1ff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED0_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_HORIZONTAL_SCALE_EN_MASK 0x200
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_HORIZONTAL_SCALE_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_VERTICAL_SCALE_EN_MASK 0x400
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_VERTICAL_SCALE_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED1_MASK 0x800
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED1_SHIFT 0xb
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_HORIZONTAL_ROUNDING_MASK 0x3000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_HORIZONTAL_ROUNDING_SHIFT 0xc
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED2_MASK 0x4000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED2_SHIFT 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_VERTICAL_ROUNDING_MASK 0x18000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_VERTICAL_ROUNDING_SHIFT 0xf
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED3_MASK 0x20000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED3_SHIFT 0x11
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_HORIZONTAL_TERMINATION_EN_MASK 0x40000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_HORIZONTAL_TERMINATION_EN_SHIFT 0x12
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_VERTICAL_TERMINATION_EN_MASK 0x80000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_VERTICAL_TERMINATION_EN_SHIFT 0x13
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED4_MASK 0xfff00000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG_UNUSED4_SHIFT 0x14

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG 0x6068  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_HEIGHT_MASK 0x3fff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_WIDTH_MASK 0x3fff0000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_INPUT_WIDTH_SHIFT 0x10
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG 0x606c  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG_PHASE_STEP_H_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG_PHASE_STEP_H_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG_UNUSED0_MASK 0x20000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG_UNUSED0_SHIFT 0x1d
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG_H_INTERP_RESO_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG_H_INTERP_RESO_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_PHASE_CFG 0x6070  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_PHASE_CFG_PHASE_INIT_H_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_PHASE_CFG_PHASE_INIT_H_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_PHASE_CFG_UNUSED0_MASK 0xe0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_PHASE_CFG_UNUSED0_SHIFT 0x1d

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG 0x6074  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG_PHASE_STEP_V_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG_PHASE_STEP_V_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG_UNUSED0_MASK 0x20000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG_UNUSED0_SHIFT 0x1d
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG_V_INTERP_RESO_MASK 0xc0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG_V_INTERP_RESO_SHIFT 0x1e

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_PHASE_CFG 0x6078  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_PHASE_CFG_PHASE_INIT_V_MASK 0x1fffffff
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_PHASE_CFG_PHASE_INIT_V_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_PHASE_CFG_UNUSED0_MASK 0xe0000000
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_PHASE_CFG_UNUSED0_SHIFT 0x1d

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_TEST_BUS_CTRL 0x61f8  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_SPARE 0x61fc  /*register offset*/
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION 0x6200  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_STATUS 0x6204  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG 0x6260  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG 0x6268  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG 0x626c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG 0x6270  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG 0x6274  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG 0x6278  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG 0x627c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG 0x6280  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG 0x6284  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL 0x6288  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_SPARE 0x63fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION 0x6400  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_STATUS 0x6404  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG 0x6460  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_RND_CLAMP_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED0_MASK 0x1fe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_EN_MASK 0x200
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CROP_EN_SHIFT 0x9
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_ROUND_EN_MASK 0x400
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_ROUND_EN_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_MASK 0x800
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH0_CLAMP_EN_SHIFT 0xb
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_ROUND_EN_MASK 0x1000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_ROUND_EN_SHIFT 0xc
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_MASK 0x2000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH1_CLAMP_EN_SHIFT 0xd
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_ROUND_EN_MASK 0x4000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_ROUND_EN_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_MASK 0x8000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_CH2_CLAMP_EN_SHIFT 0xf
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG 0x6468  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_LAST_LINE_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_LAST_LINE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_FIRST_LINE_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_FIRST_LINE_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG 0x646c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_MASK 0x3fff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_LAST_PIXEL_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED0_MASK 0xc000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED0_SHIFT 0xe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_MASK 0x3fff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_FIRST_PIXEL_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED1_MASK 0xc0000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG_UNUSED1_SHIFT 0x1e

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG 0x6470  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_CH0_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG 0x6474  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_CH0_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG 0x6478  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_CH1_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG 0x647c  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_CH1_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG 0x6480  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_MASK 0x3ff
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MIN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_MASK 0x3ff0000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_CH2_CLAMP_MAX_SHIFT 0x10
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG 0x6484  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_INTERLEAVED_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_MASK 0x6
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUNDING_PATTERN_SHIFT 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_MASK 0x38
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_CH2_ROUND_OFF_BITS_SHIFT 0x3
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL 0x6488  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_TEST_EN_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_TEST_EN_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_SPARE 0x65fc  /*register offset*/
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_HW_VERSION 0x6600  /*register offset*/
#define BPS_BPS_0_BUS_RD_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_BUS_RD_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_BUS_RD_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_BUS_RD_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_BUS_RD_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_BUS_RD_HW_CAPABILITY 0x6604  /*register offset*/
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_REG_MASK 0xff
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_REG_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_UBWC_MASK 0xff00
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_UBWC_SHIFT 0x8
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_LITE_MASK 0xff0000
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_LITE_SHIFT 0x10
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_FEATURE_MASK 0xff000000
#define BPS_BPS_0_BUS_RD_HW_CAPABILITY_FEATURE_SHIFT 0x18

#define regBPS_BPS_0_BUS_RD_INPUT_IF_SW_RESET 0x6608  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_SW_RESET_RESET_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_SW_RESET_RESET_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_SW_RESET_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_RD_INPUT_IF_SW_RESET_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_INPUT_IF_CGC_OVERRIDE 0x660c  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIDE_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_CGC_OVERRIDE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_RD_INPUT_IF_CGC_OVERRIDE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK 0x6610  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_REG_UPDATE_DONE_MASK 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RD_CLIENT_BUF_DONE_MASK 0x4
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_CCIF_VIOLATION_MASK 0x10000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_INFO_CCIF_VIOLATION_SHIFT 0x10
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED1_MASK 0xfffe0000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK_UNUSED1_SHIFT 0x11

#define regBPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR 0x6614  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_REG_UPDATE_DONE_MASK 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RD_CLIENT_BUF_DONE_MASK 0x4
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_CCIF_VIOLATION_MASK 0x10000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_INFO_CCIF_VIOLATION_SHIFT 0x10
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED1_MASK 0xfffe0000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR_UNUSED1_SHIFT 0x11

#define regBPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD 0x6618  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_CLEAR_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_CLEAR_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED0_MASK 0xe
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_SET_MASK 0x10
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_SET_SHIFT 0x4
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regBPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS 0x661c  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_REG_UPDATE_DONE_MASK 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RD_CLIENT_BUF_DONE_MASK 0x4
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_CCIF_VIOLATION_MASK 0x10000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_INFO_CCIF_VIOLATION_SHIFT 0x10
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED1_MASK 0xfffe0000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS_UNUSED1_SHIFT 0x11

#define regBPS_BPS_0_BUS_RD_INPUT_IF_CMD 0x6620  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_GO_CMD_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_GO_CMD_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_ICA_EN_MASK 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_ICA_EN_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_UNUSED0_MASK 0x4
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_STATIC_PRG_MASK 0x8
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_STATIC_PRG_SHIFT 0x3
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_UNUSED1_MASK 0xfffffff0
#define BPS_BPS_0_BUS_RD_INPUT_IF_CMD_UNUSED1_SHIFT 0x4

#define regBPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET 0x6624  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_RST_DONE_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_RST_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_REG_UPDATE_DONE_MASK 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_REG_UPDATE_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_RD_CLIENT_BUF_DONE_MASK 0x4
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_RD_CLIENT_BUF_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_UNUSED0_MASK 0xfff8
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_UNUSED0_SHIFT 0x3
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_CCIF_VIOLATION_MASK 0x10000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_INFO_CCIF_VIOLATION_SHIFT 0x10
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_UNUSED1_MASK 0xfffe0000
#define BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET_UNUSED1_SHIFT 0x11

#define regBPS_BPS_0_BUS_RD_INPUT_IF_MISR_RESET 0x662c  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_MISR_RESET_RESET_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_MISR_RESET_RESET_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_MISR_RESET_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_RD_INPUT_IF_MISR_RESET_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_INPUT_IF_SECURITY_CFG 0x6630  /*register offset*/
#define BPS_BPS_0_BUS_RD_INPUT_IF_SECURITY_CFG_ENABLE_MASK 0x1
#define BPS_BPS_0_BUS_RD_INPUT_IF_SECURITY_CFG_ENABLE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_INPUT_IF_SECURITY_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_RD_INPUT_IF_SECURITY_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_PWR_ISO_CFG 0x6634  /*register offset*/
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_PWR_ISO_ENABLE_MASK 0x1
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_PWR_ISO_ENABLE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_UNUSED0_MASK 0x2
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_PWR_ISO_PATGEN_SELECT_MASK 0xc
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_PWR_ISO_PATGEN_SELECT_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_UNUSED1_MASK 0x10
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_UNUSED1_SHIFT 0x4
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_PWR_ISO_BPP_SELECT_MASK 0x60
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_PWR_ISO_BPP_SELECT_SHIFT 0x5
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_UNUSED2_MASK 0xffffff80
#define BPS_BPS_0_BUS_RD_PWR_ISO_CFG_UNUSED2_SHIFT 0x7

#define regBPS_BPS_0_BUS_RD_PWR_ISO_SEED 0x6638  /*register offset*/
#define BPS_BPS_0_BUS_RD_PWR_ISO_SEED_PWR_ISO_PATGEN_SEED_MASK 0xffffffff
#define BPS_BPS_0_BUS_RD_PWR_ISO_SEED_PWR_ISO_PATGEN_SEED_SHIFT 0x0

#define regBPS_BPS_0_BUS_RD_TEST_BUS_CTRL 0x6648  /*register offset*/
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_MASK 0x1f0
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_SHIFT 0x4
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_MASK 0xfe00
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_SHIFT 0x9
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_BUS_RD_TEST_BUS_CTRL_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_BUS_RD_SPARE 0x664c  /*register offset*/
#define BPS_BPS_0_BUS_RD_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_BUS_RD_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_RD_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_CLIENT_0_CORE_CFG 0x6650  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_CORE_CFG_CLIENT_EN_MASK 0x1
#define BPS_BPS_0_BUS_RD_CLIENT_0_CORE_CFG_CLIENT_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_CORE_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_RD_CLIENT_0_CORE_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA 0x6654  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_MASK 0x3
#define BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_PIXEL_PATTERN_MASK 0xfc
#define BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_PIXEL_PATTERN_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_UNUSED0_MASK 0xffffff00
#define BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_UNUSED0_SHIFT 0x8

#define regBPS_BPS_0_BUS_RD_CLIENT_0_ADDR_IMAGE 0x6658  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_RD_CLIENT_0_RD_BUFFER_SIZE 0x665c  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_WIDTH_MASK 0xffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_WIDTH_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_HEIGHT_MASK 0xffff0000
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_BUFFER_SIZE_HEIGHT_SHIFT 0x10

#define regBPS_BPS_0_BUS_RD_CLIENT_0_RD_STRIDE 0x6660  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_STRIDE_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_STRIDE_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_RD_CLIENT_0_RD_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0 0x6664  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MASK 0x1f
#define BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_MASK 0x20
#define BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_SHIFT 0x5
#define BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION 0x6678  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_BUFF_SIZE_MASK 0xffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_BUFF_SIZE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_RD_CLIENT_0_BURST_LIMIT_CFG 0x6680  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_BURST_LENGTH_MAX_MASK 0xf
#define BPS_BPS_0_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_BURST_LENGTH_MAX_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_RD_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0 0x6684  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0_SAMP_MODE_MASK 0x3
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0_SAMP_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0_ENABLE_MASK 0x4
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0_ENABLE_SHIFT 0x2
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1 0x6688  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_RD_CLIENT_0_MISR_RD_VAL 0x668c  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_RD_VAL_MISR_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_MISR_RD_VAL_MISR_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG 0x6690  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_0 0x6694  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_1 0x6698  /*register offset*/
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_HW_VERSION 0x6800  /*register offset*/
#define BPS_BPS_0_BUS_WR_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_BUS_WR_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_BUS_WR_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_BUS_WR_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_BUS_WR_HW_CAPABILITY 0x6804  /*register offset*/
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_FEATURE_MASK 0xff
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_FEATURE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_LITE_MASK 0xff00
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_LITE_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_UBWC_MASK 0xff0000
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_UBWC_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_REG_MASK 0xff000000
#define BPS_BPS_0_BUS_WR_HW_CAPABILITY_REG_SHIFT 0x18

#define regBPS_BPS_0_BUS_WR_INPUT_IF_SW_RESET 0x6808  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_SW_RESET_SW_RESET_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_SW_RESET_SW_RESET_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_SW_RESET_UNUSED0_MASK 0xffffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_SW_RESET_UNUSED0_SHIFT 0x7

#define regBPS_BPS_0_BUS_WR_INPUT_IF_CGC_OVERRIDE 0x680c  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIGE_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIGE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_CGC_OVERRIDE_UNUSED0_MASK 0xffffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_CGC_OVERRIDE_UNUSED0_SHIFT 0x7

#define regBPS_BPS_0_BUS_WR_INPUT_IF_COMPOSITE_MASK_0 0x6810  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_MASK_VEC_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_MASK_VEC_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_UNUSED0_MASK 0xffffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_UNUSED0_SHIFT 0x7

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0 0x6844  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_RESET_DONE_MASK 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_RESET_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP0_BUF_DONE_MASK 0x20
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP0_BUF_DONE_SHIFT 0x5
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP1_BUF_DONE_MASK 0x40
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP1_BUF_DONE_SHIFT 0x6
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP2_BUF_DONE_MASK 0x80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP2_BUF_DONE_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP3_BUF_DONE_MASK 0x100
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP3_BUF_DONE_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP4_BUF_DONE_MASK 0x200
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP4_BUF_DONE_SHIFT 0x9
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP5_BUF_DONE_MASK 0x400
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP5_BUF_DONE_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_ERROR_MASK 0x800
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_ERROR_SHIFT 0xb
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_OVERWRITE_MASK 0x1000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_OVERWRITE_SHIFT 0xc
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_OVERFLOW_ERROR_MASK 0x2000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_OVERFLOW_ERROR_SHIFT 0xd
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_VIOLATION_MASK 0x4000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_VIOLATION_SHIFT 0xe
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_UNUSED0_MASK 0xffff8000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0_UNUSED0_SHIFT 0xf

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1 0x6848  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_WR_CLIENT_BUF_DONE_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED0_MASK 0xffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED0_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_EARLY_DONE_MASK 0x3000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_EARLY_DONE_SHIFT 0x18
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0 0x6850  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_RESET_DONE_MASK 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_RESET_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP0_BUF_DONE_MASK 0x20
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP0_BUF_DONE_SHIFT 0x5
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP1_BUF_DONE_MASK 0x40
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP1_BUF_DONE_SHIFT 0x6
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP2_BUF_DONE_MASK 0x80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP2_BUF_DONE_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP3_BUF_DONE_MASK 0x100
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP3_BUF_DONE_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP4_BUF_DONE_MASK 0x200
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP4_BUF_DONE_SHIFT 0x9
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP5_BUF_DONE_MASK 0x400
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP5_BUF_DONE_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_ERROR_MASK 0x800
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_ERROR_SHIFT 0xb
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_OVERWRITE_MASK 0x1000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_OVERWRITE_SHIFT 0xc
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_OVERFLOW_ERROR_MASK 0x2000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_OVERFLOW_ERROR_SHIFT 0xd
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_VIOLATION_MASK 0x4000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_VIOLATION_SHIFT 0xe
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_UNUSED0_MASK 0xffff8000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0_UNUSED0_SHIFT 0xf

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1 0x6854  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_WR_CLIENT_BUF_DONE_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED0_MASK 0xffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED0_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_EARLY_DONE_MASK 0x3000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_EARLY_DONE_SHIFT 0x18
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0 0x685c  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_RESET_DONE_MASK 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_RESET_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP0_BUF_DONE_MASK 0x20
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP0_BUF_DONE_SHIFT 0x5
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP1_BUF_DONE_MASK 0x40
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP1_BUF_DONE_SHIFT 0x6
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP2_BUF_DONE_MASK 0x80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP2_BUF_DONE_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP3_BUF_DONE_MASK 0x100
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP3_BUF_DONE_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP4_BUF_DONE_MASK 0x200
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP4_BUF_DONE_SHIFT 0x9
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP5_BUF_DONE_MASK 0x400
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP5_BUF_DONE_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_ERROR_MASK 0x800
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_ERROR_SHIFT 0xb
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_OVERWRITE_MASK 0x1000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_OVERWRITE_SHIFT 0xc
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_OVERFLOW_ERROR_MASK 0x2000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_OVERFLOW_ERROR_SHIFT 0xd
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_VIOLATION_MASK 0x4000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_VIOLATION_SHIFT 0xe
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_UNUSED0_MASK 0xffff8000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0_UNUSED0_SHIFT 0xf

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1 0x6860  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_WR_CLIENT_BUF_DONE_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED0_MASK 0xffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED0_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_EARLY_DONE_MASK 0x3000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_EARLY_DONE_SHIFT 0x18
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD 0x6868  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_CLEAR_MASK 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_CLEAR_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED0_MASK 0xe
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_SET_MASK 0x10
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_SET_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS 0x68a8  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_FIFO_STATUS_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_FIFO_STATUS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_UNUSED0_MASK 0xffffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_UNUSED0_SHIFT 0x7

#define regBPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0 0x68ac  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0_CFG0_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0_CFG0_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1 0x68b0  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1_CFG1_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1_CFG1_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0 0x68bc  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_RESET_DONE_MASK 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_RESET_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP0_BUF_DONE_MASK 0x20
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP0_BUF_DONE_SHIFT 0x5
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP1_BUF_DONE_MASK 0x40
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP1_BUF_DONE_SHIFT 0x6
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP2_BUF_DONE_MASK 0x80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP2_BUF_DONE_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP3_BUF_DONE_MASK 0x100
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP3_BUF_DONE_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP4_BUF_DONE_MASK 0x200
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP4_BUF_DONE_SHIFT 0x9
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP5_BUF_DONE_MASK 0x400
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP5_BUF_DONE_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_ERROR_MASK 0x800
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_ERROR_SHIFT 0xb
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_OVERWRITE_MASK 0x1000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_OVERWRITE_SHIFT 0xc
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_OVERFLOW_ERROR_MASK 0x2000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_OVERFLOW_ERROR_SHIFT 0xd
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_VIOLATION_MASK 0x4000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_VIOLATION_SHIFT 0xe
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_UNUSED0_MASK 0xffff8000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0_UNUSED0_SHIFT 0xf

#define regBPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1 0x68c0  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_WR_CLIENT_BUF_DONE_MASK 0x7f
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED0_MASK 0xffff80
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED0_SHIFT 0x7
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_EARLY_DONE_MASK 0x3000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_EARLY_DONE_SHIFT 0x18
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_BUS_WR_INPUT_IF_MISR_RESET 0x68c8  /*register offset*/
#define BPS_BPS_0_BUS_WR_INPUT_IF_MISR_RESET_RESET_MASK 0x1
#define BPS_BPS_0_BUS_WR_INPUT_IF_MISR_RESET_RESET_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_INPUT_IF_MISR_RESET_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_WR_INPUT_IF_MISR_RESET_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_WR_PWR_ISO_CFG 0x68cc  /*register offset*/
#define BPS_BPS_0_BUS_WR_PWR_ISO_CFG_PWR_ISO_ENABLE_MASK 0x1
#define BPS_BPS_0_BUS_WR_PWR_ISO_CFG_PWR_ISO_ENABLE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_PWR_ISO_CFG_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_WR_PWR_ISO_CFG_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_WR_TEST_BUS_CTRL 0x691c  /*register offset*/
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_MASK 0x1f0
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_MASK 0xfe00
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_SHIFT 0x9
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_UNUSED1_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_TEST_BUS_CTRL_UNUSED1_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_SPARE 0x6920  /*register offset*/
#define BPS_BPS_0_BUS_WR_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_BUS_WR_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_WR_SPARE_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_WR_CLIENT_0_STATUS_0 0x6a00  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_STATUS_1 0x6a04  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_CFG 0x6a08  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_0_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER 0x6a0c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_FRAME_HEADER_CFG 0x6a10  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE 0x6a14  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET 0x6a18  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG 0x6a1c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG 0x6a20  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG 0x6a24  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_0_WR_STRIDE 0x6a28  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_0_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG 0x6a2c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_TILE_PER_BLK_ROW_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_TILE_PER_BLK_ROW_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_TILE_PER_BLK_COL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_TILE_PER_BLK_COL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_PARTIAL_TILE_LEFT_MASK 0x7f0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_PARTIAL_TILE_LEFT_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_PARTIAL_TILE_RIGHT_MASK 0x3f800000
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_PARTIAL_TILE_RIGHT_SHIFT 0x17
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_BUS_WR_CLIENT_0_H_INIT 0x6a30  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_H_INIT_H_INIT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_H_INIT_H_INIT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_H_INIT_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_H_INIT_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_0_V_INIT 0x6a34  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_V_INIT_V_INIT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_V_INIT_V_INIT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_V_INIT_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_V_INIT_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META 0x6a38  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META_ADDR_META_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META_ADDR_META_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META_OFFSET 0x6a3c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META_OFFSET_META_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META_OFFSET_META_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_META_STRIDE 0x6a40  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_META_STRIDE_UBWC_META_STRIDE_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_META_STRIDE_UBWC_META_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_META_STRIDE_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_META_STRIDE_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG 0x6a44  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_COMPRESS_EN_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_COMPRESS_EN_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_BANKSPREAD_EN_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_BANKSPREAD_EN_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_EN_MASK 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_EN_SHIFT 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_HIGHESTBANK_LV1_EN_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_HIGHESTBANK_LV1_EN_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_VAL_MASK 0x3e0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_VAL_SHIFT 0x5
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_MODE_SEL_MASK 0x1c00
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_MODE_SEL_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UNUSED0_MASK 0xe000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_8CHANNEL_EN_MASK 0x10000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UBWC_8CHANNEL_EN_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UNUSED1_MASK 0xfffe0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_UNUSED1_SHIFT 0x11

#define regBPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD 0x6a48  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN 0x6a4c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_BURST_LIMIT_CFG 0x6a5c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG 0x6a60  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL 0x6a64  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_0_MISR_VAL 0x6a68  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG 0x6a6c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_0 0x6a70  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_1 0x6a74  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_STATS_CTRL 0x6a78  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_STATS_CTRL_GEN_STATS_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_STATS_CTRL_GEN_STATS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_STATS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_STATS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_32B 0x6a7c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_32B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_32B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_32B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_32B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_64B 0x6a80  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_64B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_64B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_64B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_64B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_96B 0x6a84  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_96B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_96B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_96B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_96B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_128B 0x6a88  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_128B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_128B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_128B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_128B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_160B 0x6a8c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_160B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_160B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_160B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_160B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_192B 0x6a90  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_192B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_192B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_192B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_192B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_256B 0x6a94  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_256B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_256B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_256B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_256B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT 0x6aa0  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT_ENABLE_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT_ENABLE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT_COUNTER_LIMIT_MASK 0x1fe
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT_COUNTER_LIMIT_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT_UNUSED0_MASK 0xfffffe00
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT_UNUSED0_SHIFT 0x9

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1 0x6aa4  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_UBWC_VER_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_UBWC_VER_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_UNUSED0_MASK 0xe
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_LOSSY_MODE_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_LOSSY_MODE_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_UNUSED1_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1_UNUSED1_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0 0x6aa8  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_0_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_0_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED0_MASK 0xc
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_1_MASK 0x30
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_1_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED1_MASK 0xc0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED1_SHIFT 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_2_MASK 0x300
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_2_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED2_MASK 0xfc00
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED2_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_COUNT_THRESH_MIN_MASK 0x70000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_COUNT_THRESH_MIN_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED3_MASK 0x80000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED3_SHIFT 0x13
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_LOSSY_INIT_VAL_MASK 0x700000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_LOSSY_INIT_VAL_SHIFT 0x14
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED4_MASK 0x800000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED4_SHIFT 0x17
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_THRESH_PIX_SUM_DEPTH_MASK 0xf000000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_THRESH_PIX_SUM_DEPTH_SHIFT 0x18
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED5_MASK 0xf0000000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0_UNUSED5_SHIFT 0x1c

#define regBPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1 0x6aac  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_0_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_0_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_UNUSED0_MASK 0xf0
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_1_MASK 0xf00
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_1_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_UNUSED1_MASK 0xf000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_UNUSED1_SHIFT 0xc
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_2_MASK 0xf0000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_2_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_UNUSED2_MASK 0xfff00000
#define BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1_UNUSED2_SHIFT 0x14

#define regBPS_BPS_0_BUS_WR_CLIENT_1_STATUS_0 0x6b00  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_STATUS_1 0x6b04  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_CFG 0x6b08  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_1_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER 0x6b0c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_FRAME_HEADER_CFG 0x6b10  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE 0x6b14  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET 0x6b18  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG 0x6b1c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG 0x6b20  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG 0x6b24  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_1_WR_STRIDE 0x6b28  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_1_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG 0x6b2c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_TILE_PER_BLK_ROW_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_TILE_PER_BLK_ROW_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_TILE_PER_BLK_COL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_TILE_PER_BLK_COL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_PARTIAL_TILE_LEFT_MASK 0x7f0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_PARTIAL_TILE_LEFT_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_PARTIAL_TILE_RIGHT_MASK 0x3f800000
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_PARTIAL_TILE_RIGHT_SHIFT 0x17
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_UNUSED0_MASK 0xc0000000
#define BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG_UNUSED0_SHIFT 0x1e

#define regBPS_BPS_0_BUS_WR_CLIENT_1_H_INIT 0x6b30  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_H_INIT_H_INIT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_H_INIT_H_INIT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_H_INIT_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_H_INIT_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_1_V_INIT 0x6b34  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_V_INIT_V_INIT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_V_INIT_V_INIT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_V_INIT_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_V_INIT_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META 0x6b38  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META_ADDR_META_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META_ADDR_META_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META_OFFSET 0x6b3c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META_OFFSET_META_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META_OFFSET_META_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_META_STRIDE 0x6b40  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_META_STRIDE_UBWC_META_STRIDE_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_META_STRIDE_UBWC_META_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_META_STRIDE_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_META_STRIDE_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG 0x6b44  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_COMPRESS_EN_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_COMPRESS_EN_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_BANKSPREAD_EN_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_BANKSPREAD_EN_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_EN_MASK 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_EN_SHIFT 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_HIGHESTBANK_LV1_EN_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_HIGHESTBANK_LV1_EN_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_VAL_MASK 0x3e0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_HIGHESTBANKBIT_VAL_SHIFT 0x5
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_MODE_SEL_MASK 0x1c00
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_MODE_SEL_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UNUSED0_MASK 0xe000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UNUSED0_SHIFT 0xd
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_8CHANNEL_EN_MASK 0x10000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UBWC_8CHANNEL_EN_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UNUSED1_MASK 0xfffe0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_UNUSED1_SHIFT 0x11

#define regBPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD 0x6b48  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN 0x6b4c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_BURST_LIMIT_CFG 0x6b5c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG 0x6b60  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL 0x6b64  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_1_MISR_VAL 0x6b68  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG 0x6b6c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_0 0x6b70  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_1 0x6b74  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_STATS_CTRL 0x6b78  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_STATS_CTRL_GEN_STATS_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_STATS_CTRL_GEN_STATS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_STATS_CTRL_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_STATS_CTRL_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_32B 0x6b7c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_32B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_32B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_32B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_32B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_64B 0x6b80  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_64B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_64B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_64B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_64B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_96B 0x6b84  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_96B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_96B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_96B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_96B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_128B 0x6b88  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_128B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_128B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_128B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_128B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_160B 0x6b8c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_160B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_160B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_160B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_160B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_192B 0x6b90  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_192B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_192B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_192B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_192B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_256B 0x6b94  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_256B_NUM_UNITS_MASK 0x3ffff
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_256B_NUM_UNITS_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_256B_UNUSED0_MASK 0xfffc0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_256B_UNUSED0_SHIFT 0x12

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT 0x6ba0  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT_ENABLE_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT_ENABLE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT_COUNTER_LIMIT_MASK 0x1fe
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT_COUNTER_LIMIT_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT_UNUSED0_MASK 0xfffffe00
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT_UNUSED0_SHIFT 0x9

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1 0x6ba4  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_UBWC_VER_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_UBWC_VER_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_UNUSED0_MASK 0xe
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_LOSSY_MODE_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_LOSSY_MODE_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_UNUSED1_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1_UNUSED1_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0 0x6ba8  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_0_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_0_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED0_MASK 0xc
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED0_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_1_MASK 0x30
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_1_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED1_MASK 0xc0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED1_SHIFT 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_2_MASK 0x300
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_MIN_DELTA_DARK_2_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED2_MASK 0xfc00
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED2_SHIFT 0xa
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_COUNT_THRESH_MIN_MASK 0x70000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_COUNT_THRESH_MIN_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED3_MASK 0x80000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED3_SHIFT 0x13
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_LOSSY_INIT_VAL_MASK 0x700000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_LOSSY_INIT_VAL_SHIFT 0x14
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED4_MASK 0x800000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED4_SHIFT 0x17
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_THRESH_PIX_SUM_DEPTH_MASK 0xf000000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_THRESH_PIX_SUM_DEPTH_SHIFT 0x18
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED5_MASK 0xf0000000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0_UNUSED5_SHIFT 0x1c

#define regBPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1 0x6bac  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_0_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_0_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_UNUSED0_MASK 0xf0
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_UNUSED0_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_1_MASK 0xf00
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_1_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_UNUSED1_MASK 0xf000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_UNUSED1_SHIFT 0xc
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_2_MASK 0xf0000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_MIN_DELTA_BRIGHT_2_SHIFT 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_UNUSED2_MASK 0xfff00000
#define BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1_UNUSED2_SHIFT 0x14

#define regBPS_BPS_0_BUS_WR_CLIENT_2_STATUS_0 0x6c00  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_STATUS_1 0x6c04  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_CFG 0x6c08  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_2_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER 0x6c0c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_FRAME_HEADER_CFG 0x6c10  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE 0x6c14  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET 0x6c18  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG 0x6c1c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG 0x6c20  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG 0x6c24  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_2_WR_STRIDE 0x6c28  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_2_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD 0x6c48  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN 0x6c4c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_BURST_LIMIT_CFG 0x6c5c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG 0x6c60  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL 0x6c64  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_2_MISR_VAL 0x6c68  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG 0x6c6c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_0 0x6c70  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_1 0x6c74  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_STATUS_0 0x6d00  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_STATUS_1 0x6d04  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_CFG 0x6d08  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_3_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER 0x6d0c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_FRAME_HEADER_CFG 0x6d10  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE 0x6d14  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET 0x6d18  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG 0x6d1c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG 0x6d20  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG 0x6d24  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_3_WR_STRIDE 0x6d28  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_3_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD 0x6d48  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN 0x6d4c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_BURST_LIMIT_CFG 0x6d5c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG 0x6d60  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL 0x6d64  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_3_MISR_VAL 0x6d68  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG 0x6d6c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_0 0x6d70  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_1 0x6d74  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_STATUS_0 0x6e00  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_STATUS_1 0x6e04  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_CFG 0x6e08  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_4_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_4_ADDR_FRAME_HEADER 0x6e0c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_FRAME_HEADER_CFG 0x6e10  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE 0x6e14  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE_OFFSET 0x6e18  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_WIDTH_CFG 0x6e1c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_HEIGHT_CFG 0x6e20  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG 0x6e24  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_4_WR_STRIDE 0x6e28  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_4_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PERIOD 0x6e48  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PATTERN 0x6e4c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_BURST_LIMIT_CFG 0x6e5c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_4_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_4_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG 0x6e60  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_4_MISR_RD_WORD_SEL 0x6e64  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_4_MISR_VAL 0x6e68  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG 0x6e6c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_0 0x6e70  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_1 0x6e74  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_STATUS_0 0x6f00  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_STATUS_1 0x6f04  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_CFG 0x6f08  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_5_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_5_ADDR_FRAME_HEADER 0x6f0c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_FRAME_HEADER_CFG 0x6f10  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE 0x6f14  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE_OFFSET 0x6f18  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_WIDTH_CFG 0x6f1c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_HEIGHT_CFG 0x6f20  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG 0x6f24  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_5_WR_STRIDE 0x6f28  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_5_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PERIOD 0x6f48  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PATTERN 0x6f4c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_BURST_LIMIT_CFG 0x6f5c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_5_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_5_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG 0x6f60  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_5_MISR_RD_WORD_SEL 0x6f64  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_5_MISR_VAL 0x6f68  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG 0x6f6c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_0 0x6f70  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_1 0x6f74  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_STATUS_0 0x7000  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_STATUS_1 0x7004  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_CFG 0x7008  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_MODE_MASK 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_VIRTUALFRAME_MASK 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_VIRTUALFRAME_SHIFT 0x2
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_6_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_6_ADDR_FRAME_HEADER 0x700c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_FRAME_HEADER_CFG 0x7010  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE 0x7014  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE_OFFSET 0x7018  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_WIDTH_CFG 0x701c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_HEIGHT_CFG 0x7020  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG 0x7024  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regBPS_BPS_0_BUS_WR_CLIENT_6_WR_STRIDE 0x7028  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define BPS_BPS_0_BUS_WR_CLIENT_6_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regBPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PERIOD 0x7048  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PATTERN 0x704c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_BURST_LIMIT_CFG 0x705c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define BPS_BPS_0_BUS_WR_CLIENT_6_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define BPS_BPS_0_BUS_WR_CLIENT_6_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regBPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG 0x7060  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG_EN_MASK 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG_UNUSED0_SHIFT 0x3

#define regBPS_BPS_0_BUS_WR_CLIENT_6_MISR_RD_WORD_SEL 0x7064  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regBPS_BPS_0_BUS_WR_CLIENT_6_MISR_VAL 0x7068  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_VAL_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_MISR_VAL_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG 0x706c  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regBPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_0 0x7070  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regBPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_1 0x7074  /*register offset*/
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regBPS_BPS_0_QOS_HW_VERSION 0x7100  /*register offset*/
#define BPS_BPS_0_QOS_HW_VERSION_STEP_MASK 0xffff
#define BPS_BPS_0_QOS_HW_VERSION_STEP_SHIFT 0x0
#define BPS_BPS_0_QOS_HW_VERSION_REV_MASK 0xfff0000
#define BPS_BPS_0_QOS_HW_VERSION_REV_SHIFT 0x10
#define BPS_BPS_0_QOS_HW_VERSION_GEN_MASK 0xf0000000
#define BPS_BPS_0_QOS_HW_VERSION_GEN_SHIFT 0x1c

#define regBPS_BPS_0_QOS_HW_STATUS 0x7104  /*register offset*/
#define BPS_BPS_0_QOS_HW_STATUS_VIOLATION_MASK 0x1
#define BPS_BPS_0_QOS_HW_STATUS_VIOLATION_SHIFT 0x0
#define BPS_BPS_0_QOS_HW_STATUS_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_QOS_HW_STATUS_UNUSED0_SHIFT 0x1

#define regBPS_BPS_0_QOS_MODULE_CFG 0x7160  /*register offset*/
#define BPS_BPS_0_QOS_MODULE_CFG_EN_MASK 0x1
#define BPS_BPS_0_QOS_MODULE_CFG_EN_SHIFT 0x0
#define BPS_BPS_0_QOS_MODULE_CFG_UNUSED0_MASK 0xfe
#define BPS_BPS_0_QOS_MODULE_CFG_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_QOS_MODULE_CFG_STATIC_HEALTH_MASK 0xf00
#define BPS_BPS_0_QOS_MODULE_CFG_STATIC_HEALTH_SHIFT 0x8
#define BPS_BPS_0_QOS_MODULE_CFG_UNUSED1_MASK 0xf000
#define BPS_BPS_0_QOS_MODULE_CFG_UNUSED1_SHIFT 0xc
#define BPS_BPS_0_QOS_MODULE_CFG_PROC_INTERVAL_MASK 0x3ff0000
#define BPS_BPS_0_QOS_MODULE_CFG_PROC_INTERVAL_SHIFT 0x10
#define BPS_BPS_0_QOS_MODULE_CFG_UNUSED2_MASK 0xfc000000
#define BPS_BPS_0_QOS_MODULE_CFG_UNUSED2_SHIFT 0x1a

#define regBPS_BPS_0_QOS_CURVE_CFG_0 0x7168  /*register offset*/
#define BPS_BPS_0_QOS_CURVE_CFG_0_YMIN_INC_MASK 0x3ff
#define BPS_BPS_0_QOS_CURVE_CFG_0_YMIN_INC_SHIFT 0x0
#define BPS_BPS_0_QOS_CURVE_CFG_0_UNUSED0_MASK 0xfc00
#define BPS_BPS_0_QOS_CURVE_CFG_0_UNUSED0_SHIFT 0xa
#define BPS_BPS_0_QOS_CURVE_CFG_0_YEXP_YMIN_DEC_MASK 0x3ff0000
#define BPS_BPS_0_QOS_CURVE_CFG_0_YEXP_YMIN_DEC_SHIFT 0x10
#define BPS_BPS_0_QOS_CURVE_CFG_0_UNUSED1_MASK 0xfc000000
#define BPS_BPS_0_QOS_CURVE_CFG_0_UNUSED1_SHIFT 0x1a

#define regBPS_BPS_0_QOS_CURVE_CFG_1 0x716c  /*register offset*/
#define BPS_BPS_0_QOS_CURVE_CFG_1_INITIAL_DELTA_MASK 0x3ffffff
#define BPS_BPS_0_QOS_CURVE_CFG_1_INITIAL_DELTA_SHIFT 0x0
#define BPS_BPS_0_QOS_CURVE_CFG_1_UNUSED0_MASK 0xfc000000
#define BPS_BPS_0_QOS_CURVE_CFG_1_UNUSED0_SHIFT 0x1a

#define regBPS_BPS_0_QOS_WINDOW_CFG 0x7170  /*register offset*/
#define BPS_BPS_0_QOS_WINDOW_CFG_SESSION_CNT_MASK 0x3f
#define BPS_BPS_0_QOS_WINDOW_CFG_SESSION_CNT_SHIFT 0x0
#define BPS_BPS_0_QOS_WINDOW_CFG_UNUSED0_MASK 0xffffffc0
#define BPS_BPS_0_QOS_WINDOW_CFG_UNUSED0_SHIFT 0x6

#define regBPS_BPS_0_QOS_EOS_STATUS_0 0x7174  /*register offset*/
#define BPS_BPS_0_QOS_EOS_STATUS_0_EOS_ID_MASK 0x1
#define BPS_BPS_0_QOS_EOS_STATUS_0_EOS_ID_SHIFT 0x0
#define BPS_BPS_0_QOS_EOS_STATUS_0_EOS_YEXP_YMIN_MASK 0xffffffe
#define BPS_BPS_0_QOS_EOS_STATUS_0_EOS_YEXP_YMIN_SHIFT 0x1
#define BPS_BPS_0_QOS_EOS_STATUS_0_EOS_HEALTH_MASK 0xf0000000
#define BPS_BPS_0_QOS_EOS_STATUS_0_EOS_HEALTH_SHIFT 0x1c

#define regBPS_BPS_0_QOS_EOS_STATUS_1 0x7178  /*register offset*/
#define BPS_BPS_0_QOS_EOS_STATUS_1_EOS_ID_MASK 0x1
#define BPS_BPS_0_QOS_EOS_STATUS_1_EOS_ID_SHIFT 0x0
#define BPS_BPS_0_QOS_EOS_STATUS_1_UNUSED0_MASK 0xe
#define BPS_BPS_0_QOS_EOS_STATUS_1_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_QOS_EOS_STATUS_1_STRIPE_ACTIVE_CYC_MASK 0xfffffff0
#define BPS_BPS_0_QOS_EOS_STATUS_1_STRIPE_ACTIVE_CYC_SHIFT 0x4

#define regBPS_BPS_0_QOS_EOS_STATUS_2 0x717c  /*register offset*/
#define BPS_BPS_0_QOS_EOS_STATUS_2_EOS_ID_MASK 0x1
#define BPS_BPS_0_QOS_EOS_STATUS_2_EOS_ID_SHIFT 0x0
#define BPS_BPS_0_QOS_EOS_STATUS_2_UNUSED0_MASK 0xe
#define BPS_BPS_0_QOS_EOS_STATUS_2_UNUSED0_SHIFT 0x1
#define BPS_BPS_0_QOS_EOS_STATUS_2_STRIPE_IDLE_CYC_MASK 0xfffffff0
#define BPS_BPS_0_QOS_EOS_STATUS_2_STRIPE_IDLE_CYC_SHIFT 0x4

#define regBPS_BPS_0_QOS_SPARE 0x72fc  /*register offset*/
#define BPS_BPS_0_QOS_SPARE_SPARE_MASK 0x1
#define BPS_BPS_0_QOS_SPARE_SPARE_SHIFT 0x0
#define BPS_BPS_0_QOS_SPARE_UNUSED0_MASK 0xfffffffe
#define BPS_BPS_0_QOS_SPARE_UNUSED0_SHIFT 0x1

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  REVISION : 16; /* 15:0 */
    unsigned  MINOR_VERSION : 12; /* 27:16 */
    unsigned  MAJOR_VERSION : 4; /* 31:28 */
} _bps_bps_0_cdm_hw_version;

typedef union{
    _bps_bps_0_cdm_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_HW_VERSION;

typedef struct{
    unsigned  STEP : 8; /* 7:0 */
    unsigned  TIER : 8; /* 15:8 */
    unsigned  GENERATION : 8; /* 23:16 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _bps_bps_0_cdm_titan_version;

typedef union{
    _bps_bps_0_cdm_titan_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_TITAN_VERSION;

typedef struct{
    unsigned  CORE_RST_STB : 1; /* 0:0 */
    unsigned  PERF_MON_RST_STB : 1; /* 1:1 */
    unsigned  MISR_RST_STB : 1; /* 2:2 */
    unsigned  BL_FIFO_RST_STB : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_cdm_rst_cmd;

typedef union{
    _bps_bps_0_cdm_rst_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_RST_CMD;

typedef struct{
    unsigned  CDM_CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  AHB_CGC_OVERRIDE : 1; /* 1:1 */
    unsigned  RIF_CGC_OVERRIDE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_cdm_cgc_cfg;

typedef union{
    _bps_bps_0_cdm_cgc_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CGC_CFG;

typedef struct{
    unsigned  AHB_BURST_LEN : 4; /* 3:0 */
    unsigned  AHB_BURST_EN : 1; /* 4:4 */
    unsigned  UNUSED0 : 3; /* 7:5 */
    unsigned  AHB_STOP_ON_ERROR : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _bps_bps_0_cdm_core_cfg;

typedef union{
    _bps_bps_0_cdm_core_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CORE_CFG;

typedef struct{
    unsigned  CDM_EN : 1; /* 0:0 */
    unsigned  CDM_PAUSE : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_cdm_core_en;

typedef union{
    _bps_bps_0_cdm_core_en bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CORE_EN;

typedef struct{
    unsigned  AXI_BURST_LEN : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  BUS_RD_CLIENT_REQ_DATA_CNTR_MAX : 16; /* 31:16 */
} _bps_bps_0_cdm_fe_cfg;

typedef union{
    _bps_bps_0_cdm_fe_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_FE_CFG;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_INLINE_IRQ : 1; /* 1:1 */
    unsigned  INFO_BL_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  ERROR_INV_CMD : 1; /* 16:16 */
    unsigned  ERROR_OVER_FLOW : 1; /* 17:17 */
    unsigned  ERROR_AHB_BUS : 1; /* 18:18 */
    unsigned  UNUSED1 : 13; /* 31:19 */
} _bps_bps_0_cdm_irq_mask;

typedef union{
    _bps_bps_0_cdm_irq_mask bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_MASK;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_INLINE_IRQ : 1; /* 1:1 */
    unsigned  INFO_BL_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  ERROR_INV_CMD : 1; /* 16:16 */
    unsigned  ERROR_OVER_FLOW : 1; /* 17:17 */
    unsigned  ERROR_AHB_BUS : 1; /* 18:18 */
    unsigned  UNUSED1 : 13; /* 31:19 */
} _bps_bps_0_cdm_irq_clear;

typedef union{
    _bps_bps_0_cdm_irq_clear bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_CLEAR;

typedef struct{
    unsigned  IRQ_CLEAR_CMD : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_cdm_irq_clear_cmd;

typedef union{
    _bps_bps_0_cdm_irq_clear_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_CLEAR_CMD;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_INLINE_IRQ : 1; /* 1:1 */
    unsigned  INFO_BL_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  ERROR_INV_CMD : 1; /* 16:16 */
    unsigned  ERROR_OVER_FLOW : 1; /* 17:17 */
    unsigned  ERROR_AHB_BUS : 1; /* 18:18 */
    unsigned  UNUSED1 : 13; /* 31:19 */
} _bps_bps_0_cdm_irq_set;

typedef union{
    _bps_bps_0_cdm_irq_set bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_SET;

typedef struct{
    unsigned  IRQ_SET_CMD : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_cdm_irq_set_cmd;

typedef union{
    _bps_bps_0_cdm_irq_set_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_SET_CMD;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_INLINE_IRQ : 1; /* 1:1 */
    unsigned  INFO_BL_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  ERROR_INV_CMD : 1; /* 16:16 */
    unsigned  ERROR_OVER_FLOW : 1; /* 17:17 */
    unsigned  ERROR_AHB_BUS : 1; /* 18:18 */
    unsigned  UNUSED1 : 13; /* 31:19 */
} _bps_bps_0_cdm_irq_status;

typedef union{
    _bps_bps_0_cdm_irq_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_STATUS;

typedef struct{
    unsigned  BASE : 32; /* 31:0 */
} _bps_bps_0_cdm_bl_fifo_base_reg;

typedef union{
    _bps_bps_0_cdm_bl_fifo_base_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_BASE_REG;

typedef struct{
    unsigned  LEN : 20; /* 19:0 */
    unsigned  UNUSED0 : 4; /* 23:20 */
    unsigned  TAG : 8; /* 31:24 */
} _bps_bps_0_cdm_bl_fifo_len_reg;

typedef union{
    _bps_bps_0_cdm_bl_fifo_len_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_LEN_REG;

typedef struct{
    unsigned  COMMIT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_cdm_bl_fifo_store_reg;

typedef union{
    _bps_bps_0_cdm_bl_fifo_store_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_STORE_REG;

typedef struct{
    unsigned  REQ_SIZE : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_cdm_bl_fifo_cfg;

typedef union{
    _bps_bps_0_cdm_bl_fifo_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_CFG;

typedef struct{
    unsigned  FIFO_OFFSET : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_cdm_bl_fifo_rb;

typedef union{
    _bps_bps_0_cdm_bl_fifo_rb bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_RB;

typedef struct{
    unsigned  BASE : 32; /* 31:0 */
} _bps_bps_0_cdm_bl_fifo_base_rb;

typedef union{
    _bps_bps_0_cdm_bl_fifo_base_rb bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_BASE_RB;

typedef struct{
    unsigned  LEN : 20; /* 19:0 */
    unsigned  UNUSED0 : 4; /* 23:20 */
    unsigned  TAG : 8; /* 31:24 */
} _bps_bps_0_cdm_bl_fifo_len_rb;

typedef union{
    _bps_bps_0_cdm_bl_fifo_len_rb bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_LEN_RB;

typedef struct{
    unsigned  PENDING_REQ : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _bps_bps_0_cdm_bl_fifo_pending_req_rb;

typedef union{
    _bps_bps_0_cdm_bl_fifo_pending_req_rb bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BL_FIFO_PENDING_REQ_RB;

typedef struct{
    unsigned  VALUE : 32; /* 31:0 */
} _bps_bps_0_cdm_irq_usr_data;

typedef union{
    _bps_bps_0_cdm_irq_usr_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_IRQ_USR_DATA;

typedef struct{
    unsigned  MASK : 8; /* 7:0 */
    unsigned  ID : 8; /* 15:8 */
    unsigned  WAITING : 1; /* 16:16 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_cdm_wait_status;

typedef union{
    _bps_bps_0_cdm_wait_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_WAIT_STATUS;

typedef struct{
    unsigned  WAITING : 32; /* 31:0 */
} _bps_bps_0_cdm_comp_wait_status0;

typedef union{
    _bps_bps_0_cdm_comp_wait_status0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_COMP_WAIT_STATUS0;

typedef struct{
    unsigned  WAITING : 32; /* 31:0 */
} _bps_bps_0_cdm_comp_wait_status1;

typedef union{
    _bps_bps_0_cdm_comp_wait_status1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_COMP_WAIT_STATUS1;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_0_reg;

typedef union{
    _bps_bps_0_cdm_scratch_0_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_0_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_1_reg;

typedef union{
    _bps_bps_0_cdm_scratch_1_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_1_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_2_reg;

typedef union{
    _bps_bps_0_cdm_scratch_2_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_2_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_3_reg;

typedef union{
    _bps_bps_0_cdm_scratch_3_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_3_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_4_reg;

typedef union{
    _bps_bps_0_cdm_scratch_4_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_4_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_5_reg;

typedef union{
    _bps_bps_0_cdm_scratch_5_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_5_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_6_reg;

typedef union{
    _bps_bps_0_cdm_scratch_6_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_6_REG;

typedef struct{
    unsigned  GP_REG : 32; /* 31:0 */
} _bps_bps_0_cdm_scratch_7_reg;

typedef union{
    _bps_bps_0_cdm_scratch_7_reg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SCRATCH_7_REG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_cdm_last_ahb_addr;

typedef union{
    _bps_bps_0_cdm_last_ahb_addr bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_LAST_AHB_ADDR;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_cdm_last_ahb_data;

typedef union{
    _bps_bps_0_cdm_last_ahb_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_LAST_AHB_DATA;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  LOG_AHB : 1; /* 8:8 */
    unsigned  UNUSED1 : 7; /* 15:9 */
    unsigned  BL_FIFO_RD_EN : 1; /* 16:16 */
    unsigned  UNUSED2 : 15; /* 31:17 */
} _bps_bps_0_cdm_core_dbug;

typedef union{
    _bps_bps_0_cdm_core_dbug bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CORE_DBUG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_cdm_last_ahb_err_addr;

typedef union{
    _bps_bps_0_cdm_last_ahb_err_addr bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_LAST_AHB_ERR_ADDR;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_cdm_last_ahb_err_data;

typedef union{
    _bps_bps_0_cdm_last_ahb_err_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_LAST_AHB_ERR_DATA;

typedef struct{
    unsigned  BASE : 32; /* 31:0 */
} _bps_bps_0_cdm_current_bl_base;

typedef union{
    _bps_bps_0_cdm_current_bl_base bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CURRENT_BL_BASE;

typedef struct{
    unsigned  LEN : 20; /* 19:0 */
    unsigned  UNUSED0 : 4; /* 23:20 */
    unsigned  TAG : 8; /* 31:24 */
} _bps_bps_0_cdm_current_bl_len;

typedef union{
    _bps_bps_0_cdm_current_bl_len bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CURRENT_BL_LEN;

typedef struct{
    unsigned  VALUE : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _bps_bps_0_cdm_current_used_ahb_base;

typedef union{
    _bps_bps_0_cdm_current_used_ahb_base bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_CURRENT_USED_AHB_BASE;

typedef struct{
    unsigned  VALUE : 32; /* 31:0 */
} _bps_bps_0_cdm_debug_status;

typedef union{
    _bps_bps_0_cdm_debug_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_DEBUG_STATUS;

typedef struct{
    unsigned  FE_SAMP_MODE : 2; /* 1:0 */
    unsigned  FE_ENABLE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_cdm_bus_misr_cfg_0;

typedef union{
    _bps_bps_0_cdm_bus_misr_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BUS_MISR_CFG_0;

typedef struct{
    unsigned  MISR_RD_WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_cdm_bus_misr_cfg_1;

typedef union{
    _bps_bps_0_cdm_bus_misr_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BUS_MISR_CFG_1;

typedef struct{
    unsigned  MISR_VAL : 32; /* 31:0 */
} _bps_bps_0_cdm_bus_misr_rd_val;

typedef union{
    _bps_bps_0_cdm_bus_misr_rd_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_BUS_MISR_RD_VAL;

typedef struct{
    unsigned  PERF_MON_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_cdm_perf_mon_ctrl;

typedef union{
    _bps_bps_0_cdm_perf_mon_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_PERF_MON_CTRL;

typedef struct{
    unsigned  TOTAL_CYCLES : 32; /* 31:0 */
} _bps_bps_0_cdm_perf_mon_0;

typedef union{
    _bps_bps_0_cdm_perf_mon_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_PERF_MON_0;

typedef struct{
    unsigned  TOTAL_CYCLES : 32; /* 31:0 */
} _bps_bps_0_cdm_perf_mon_1;

typedef union{
    _bps_bps_0_cdm_perf_mon_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_PERF_MON_1;

typedef struct{
    unsigned  TOTAL_CYCLES : 32; /* 31:0 */
} _bps_bps_0_cdm_perf_mon_2;

typedef union{
    _bps_bps_0_cdm_perf_mon_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_PERF_MON_2;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_cdm_spare;

typedef union{
    _bps_bps_0_cdm_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CDM_SPARE;

typedef struct{
    unsigned  REVISION : 16; /* 15:0 */
    unsigned  MINOR_VERSION : 12; /* 27:16 */
    unsigned  MAJOR_VERSION : 4; /* 31:28 */
} _bps_bps_0_hw_version;

typedef union{
    _bps_bps_0_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_HW_VERSION;

typedef struct{
    unsigned  STEP : 8; /* 7:0 */
    unsigned  TIER : 8; /* 15:8 */
    unsigned  GENERATION : 8; /* 23:16 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _bps_bps_0_titan_version;

typedef union{
    _bps_bps_0_titan_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_TITAN_VERSION;

typedef struct{
    unsigned  HW_MOD_RST : 1; /* 0:0 */
    unsigned  SW_REG_RST : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_rst_cmd;

typedef union{
    _bps_bps_0_rst_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_RST_CMD;

typedef struct{
    unsigned  RST_DONE_IRQ : 1; /* 0:0 */
    unsigned  WE_IRQ : 1; /* 1:1 */
    unsigned  FE_IRQ : 1; /* 2:2 */
    unsigned  BPS_IRQ : 1; /* 3:3 */
    unsigned  IDLE_IRQ : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_irq_status;

typedef union{
    _bps_bps_0_irq_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_IRQ_STATUS;

typedef struct{
    unsigned  RST_DONE_IRQ_MASK : 1; /* 0:0 */
    unsigned  WE_IRQ_MASK : 1; /* 1:1 */
    unsigned  FE_IRQ_MASK : 1; /* 2:2 */
    unsigned  BPS_IRQ_MASK : 1; /* 3:3 */
    unsigned  IDLE_IRQ_MASK : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_irq_mask;

typedef union{
    _bps_bps_0_irq_mask bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_IRQ_MASK;

typedef struct{
    unsigned  RST_DONE_IRQ_CLEAR : 1; /* 0:0 */
    unsigned  WE_IRQ_CLEAR : 1; /* 1:1 */
    unsigned  FE_IRQ_CLEAR : 1; /* 2:2 */
    unsigned  BPS_IRQ_CLEAR : 1; /* 3:3 */
    unsigned  IDLE_IRQ_CLEAR : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_irq_clear;

typedef union{
    _bps_bps_0_irq_clear bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_IRQ_CLEAR;

typedef struct{
    unsigned  RST_DONE_IRQ_SET : 1; /* 0:0 */
    unsigned  WE_IRQ_SET : 1; /* 1:1 */
    unsigned  FE_IRQ_SET : 1; /* 2:2 */
    unsigned  BPS_IRQ_SET : 1; /* 3:3 */
    unsigned  IDLE_IRQ_SET : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_irq_set;

typedef union{
    _bps_bps_0_irq_set bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_IRQ_SET;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _bps_bps_0_irq_cmd;

typedef union{
    _bps_bps_0_irq_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_IRQ_CMD;

typedef struct{
    unsigned  BPS_CORE_CLK_CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  FE_CORE_CLK_CGC_OVERRIDE : 1; /* 1:1 */
    unsigned  WE_CORE_CLK_CGC_OVERRIDE : 1; /* 2:2 */
    unsigned  CLC_PEDESTAL_CORE_CLK_CGC_OVERRIDE : 1; /* 3:3 */
    unsigned  CLC_LINEARIZATION_CORE_CLK_CGC_OVERRIDE : 1; /* 4:4 */
    unsigned  CLC_BPC_PDPC_CORE_CLK_CGC_OVERRIDE : 1; /* 5:5 */
    unsigned  CLC_HDR_RECON_CORE_CLK_CGC_OVERRIDE : 1; /* 6:6 */
    unsigned  CLC_HDR_MAC_CORE_CLK_CGC_OVERRIDE : 1; /* 7:7 */
    unsigned  CLC_GIC_CORE_CLK_CGC_OVERRIDE : 1; /* 8:8 */
    unsigned  CLC_ABF_CORE_CLK_CGC_OVERRIDE : 1; /* 9:9 */
    unsigned  CLC_LENS_ROLLOFF_CORE_CLK_CGC_OVERRIDE : 1; /* 10:10 */
    unsigned  CLC_DEMO_CORE_CLK_CGC_OVERRIDE : 1; /* 11:11 */
    unsigned  CLC_BG_STATS_CORE_CLK_CGC_OVERRIDE : 1; /* 12:12 */
    unsigned  CLC_HDR_BHIST_STATS_CORE_CLK_CGC_OVERRIDE : 1; /* 13:13 */
    unsigned  CLC_COLOR_CORRECT_CORE_CLK_CGC_OVERRIDE : 1; /* 14:14 */
    unsigned  CLC_GTM_CORE_CLK_CGC_OVERRIDE : 1; /* 15:15 */
    unsigned  CLC_GLUT_CORE_CLK_CGC_OVERRIDE : 1; /* 16:16 */
    unsigned  CLC_COLOR_XFORM_CORE_CLK_CGC_OVERRIDE : 1; /* 17:17 */
    unsigned  CLC_DOWNSCALE_MN_Y_CORE_CLK_CGC_OVERRIDE : 1; /* 18:18 */
    unsigned  CLC_DOWNSCALE_MN_C_CORE_CLK_CGC_OVERRIDE : 1; /* 19:19 */
    unsigned  CLC_DOWNSCALE_4TO1_Y_CORE_CLK_CGC_OVERRIDE : 1; /* 20:20 */
    unsigned  CLC_DOWNSCALE_4TO1_C_CORE_CLK_CGC_OVERRIDE : 1; /* 21:21 */
    unsigned  CLC_R2PD_CORE_CLK_CGC_OVERRIDE : 1; /* 22:22 */
    unsigned  CLC_CROP_RND_CLAMP_CORE_CLK_CGC_OVERRIDE : 1; /* 23:23 */
    unsigned  CLC_PD2R_CORE_CLK_CGC_OVERRIDE : 1; /* 24:24 */
    unsigned  CLC_DEMUX_CORE_CLK_CGC_OVERRIDE : 1; /* 25:25 */
    unsigned  CLC_HNR_CORE_CLK_CGC_OVERRIDE : 1; /* 26:26 */
    unsigned  UNUSED0 : 5; /* 31:27 */
} _bps_bps_0_core_clk_cfg_0;

typedef union{
    _bps_bps_0_core_clk_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CORE_CLK_CFG_0;

typedef struct{
    unsigned  BPS_AHB_CLK_CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_core_clk_cfg_1;

typedef union{
    _bps_bps_0_core_clk_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CORE_CLK_CFG_1;

typedef struct{
    unsigned  BPS_NOC_CLK_CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_core_clk_cfg_2;

typedef union{
    _bps_bps_0_core_clk_cfg_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CORE_CLK_CFG_2;

typedef struct{
    unsigned  INPUT_FORMAT : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  OUTPUT_FORMAT_FULL_DS4 : 1; /* 4:4 */
    unsigned  UNUSED1 : 3; /* 7:5 */
    unsigned  OUTPUT_FORMAT_PACK_BAYER_ARGB : 3; /* 10:8 */
    unsigned  UNUSED2 : 5; /* 15:11 */
    unsigned  ARGB_ALPHA : 16; /* 31:16 */
} _bps_bps_0_core_cfg;

typedef union{
    _bps_bps_0_core_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CORE_CFG;

typedef struct{
    unsigned  VIOLATION_STATUS : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_violation_status;

typedef union{
    _bps_bps_0_violation_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_VIOLATION_STATUS;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_spare;

typedef union{
    _bps_bps_0_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_pd2r_hw_version;

typedef union{
    _bps_bps_0_clc_pd2r_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PD2R_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pd2r_hw_status;

typedef union{
    _bps_bps_0_clc_pd2r_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PD2R_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  PACK_MODE : 1; /* 8:8 */
    unsigned  UNUSED1 : 23; /* 31:9 */
} _bps_bps_0_clc_pd2r_module_cfg;

typedef union{
    _bps_bps_0_clc_pd2r_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PD2R_MODULE_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_pd2r_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_pd2r_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PD2R_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pd2r_spare;

typedef union{
    _bps_bps_0_clc_pd2r_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PD2R_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_demux_hw_version;

typedef union{
    _bps_bps_0_clc_demux_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_HW_VERSION;

typedef struct{
    unsigned  VIOLATION_CH_Y : 1; /* 0:0 */
    unsigned  VIOLATION_CH_UV : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_demux_hw_status;

typedef union{
    _bps_bps_0_clc_demux_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  PERIOD : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _bps_bps_0_clc_demux_module_cfg;

typedef union{
    _bps_bps_0_clc_demux_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_MODULE_CFG;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_clc_demux_demux_even_line_cfg;

typedef union{
    _bps_bps_0_clc_demux_demux_even_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_DEMUX_EVEN_LINE_CFG;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_clc_demux_demux_odd_line_cfg;

typedef union{
    _bps_bps_0_clc_demux_demux_odd_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_DEMUX_ODD_LINE_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_demux_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_demux_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_demux_spare;

typedef union{
    _bps_bps_0_clc_demux_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMUX_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_pedestal_hw_version;

typedef union{
    _bps_bps_0_clc_pedestal_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pedestal_hw_status;

typedef union{
    _bps_bps_0_clc_pedestal_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_HW_STATUS;

typedef struct{
    unsigned  ADDR : 8; /* 7:0 */
    unsigned  UNUSED0 : 12; /* 19:8 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_pedestal_dmi_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_pedestal_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_1;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_2;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_3;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_4;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_5;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_6;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_7;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_8;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_9;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_10;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_11;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_12;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_13;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_14;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_pedestal_dmi_data_15;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_pedestal_dmi_cmd;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pedestal_dmi_status;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pedestal_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pedestal_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  SCALE_BYPASS : 1; /* 8:8 */
    unsigned  UNUSED1 : 3; /* 11:9 */
    unsigned  NUM_SUBBLOCKS : 2; /* 13:12 */
    unsigned  UNUSED2 : 2; /* 15:14 */
    unsigned  INIT_BLOCK_X : 4; /* 19:16 */
    unsigned  INIT_BLOCK_Y : 4; /* 23:20 */
    unsigned  INIT_SUBBLOCK_X : 3; /* 26:24 */
    unsigned  UNUSED3 : 1; /* 27:27 */
    unsigned  INIT_SUBBLOCK_Y : 3; /* 30:28 */
    unsigned  UNUSED4 : 1; /* 31:31 */
} _bps_bps_0_clc_pedestal_module_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_CFG;

typedef struct{
    unsigned  BLOCK_WIDTH : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  BLOCK_HEIGHT : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_pedestal_module_1_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_1_CFG;

typedef struct{
    unsigned  SUBBLOCK_WIDTH : 11; /* 10:0 */
    unsigned  UNUSED0 : 1; /* 11:11 */
    unsigned  INV_SUBBLOCK_WIDTH : 17; /* 28:12 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_pedestal_module_2_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_2_CFG;

typedef struct{
    unsigned  SUBBLOCK_HEIGHT : 10; /* 9:0 */
    unsigned  UNUSED0 : 2; /* 11:10 */
    unsigned  INV_SUBBLOCK_HEIGHT : 17; /* 28:12 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_pedestal_module_3_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_3_CFG;

typedef struct{
    unsigned  INIT_PIXEL_X : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  INIT_PIXEL_Y : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_pedestal_module_4_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_4_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_4_CFG;

typedef struct{
    unsigned  INIT_YDELTA : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _bps_bps_0_clc_pedestal_module_5_cfg;

typedef union{
    _bps_bps_0_clc_pedestal_module_5_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_MODULE_5_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_pedestal_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_pedestal_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_pedestal_spare;

typedef union{
    _bps_bps_0_clc_pedestal_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_PEDESTAL_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_linearization_hw_version;

typedef union{
    _bps_bps_0_clc_linearization_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_hw_status;

typedef union{
    _bps_bps_0_clc_linearization_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_HW_STATUS;

typedef struct{
    unsigned  ADDR : 6; /* 5:0 */
    unsigned  UNUSED0 : 14; /* 19:6 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_linearization_dmi_cfg;

typedef union{
    _bps_bps_0_clc_linearization_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_linearization_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_1;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_2;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_3;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_4;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_5;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_6;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_7;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_8;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_9;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_10;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_11;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_12;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_13;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_14;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_linearization_dmi_data_15;

typedef union{
    _bps_bps_0_clc_linearization_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_linearization_dmi_cmd;

typedef union{
    _bps_bps_0_clc_linearization_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_dmi_status;

typedef union{
    _bps_bps_0_clc_linearization_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_linearization_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_linearization_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_module_cfg;

typedef union{
    _bps_bps_0_clc_linearization_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_MODULE_CFG;

typedef struct{
    unsigned  P0 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P1 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_r_0_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_r_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_0_CFG;

typedef struct{
    unsigned  P2 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P3 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_r_1_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_r_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_1_CFG;

typedef struct{
    unsigned  P4 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P5 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_r_2_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_r_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_2_CFG;

typedef struct{
    unsigned  P6 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P7 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_r_3_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_r_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_R_3_CFG;

typedef struct{
    unsigned  P0 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P1 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gr_0_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gr_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_0_CFG;

typedef struct{
    unsigned  P2 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P3 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gr_1_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gr_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_1_CFG;

typedef struct{
    unsigned  P4 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P5 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gr_2_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gr_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_2_CFG;

typedef struct{
    unsigned  P6 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P7 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gr_3_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gr_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GR_3_CFG;

typedef struct{
    unsigned  P0 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P1 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_b_0_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_b_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_0_CFG;

typedef struct{
    unsigned  P2 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P3 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_b_1_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_b_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_1_CFG;

typedef struct{
    unsigned  P4 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P5 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_b_2_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_b_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_2_CFG;

typedef struct{
    unsigned  P6 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P7 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_b_3_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_b_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_B_3_CFG;

typedef struct{
    unsigned  P0 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P1 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gb_0_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gb_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_0_CFG;

typedef struct{
    unsigned  P2 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P3 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gb_1_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gb_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_1_CFG;

typedef struct{
    unsigned  P4 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P5 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gb_2_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gb_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_2_CFG;

typedef struct{
    unsigned  P6 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  P7 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_linearization_kneepoint_gb_3_cfg;

typedef union{
    _bps_bps_0_clc_linearization_kneepoint_gb_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_KNEEPOINT_GB_3_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_linearization_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_linearization_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_linearization_spare;

typedef union{
    _bps_bps_0_clc_linearization_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LINEARIZATION_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_bpc_pdpc_hw_version;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  OVERFLOW_ERROR : 1; /* 1:1 */
    unsigned  OVERWRITE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_bpc_pdpc_hw_status;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_HW_STATUS;

typedef struct{
    unsigned  ADDR : 6; /* 5:0 */
    unsigned  UNUSED0 : 14; /* 19:6 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_bpc_pdpc_dmi_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_bpc_pdpc_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_1;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_2;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_3;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_4;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_5;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_6;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_7;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_8;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_9;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_10;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_11;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_12;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_13;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_14;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_dmi_data_15;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_bpc_pdpc_dmi_cmd;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_bpc_pdpc_dmi_status;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_bpc_pdpc_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_bpc_pdpc_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 6; /* 7:2 */
    unsigned  PDAF_PDPC_EN : 1; /* 8:8 */
    unsigned  BPC_EN : 1; /* 9:9 */
    unsigned  LEFT_CROP_EN : 1; /* 10:10 */
    unsigned  RIGHT_CROP_EN : 1; /* 11:11 */
    unsigned  HOT_PIXEL_CORRECTION_DISABLE : 1; /* 12:12 */
    unsigned  COLD_PIXEL_CORRECTION_DISABLE : 1; /* 13:13 */
    unsigned  USING_CROSS_CHANNEL_EN : 1; /* 14:14 */
    unsigned  REMOVE_ALONG_EDGE_EN : 1; /* 15:15 */
    unsigned  BAYER_PATTERN : 2; /* 17:16 */
    unsigned  PDAF_HDR_SELECTION : 3; /* 20:18 */
    unsigned  PDAF_ZZHDR_FIRST_RB_EXP : 1; /* 21:21 */
    unsigned  CHANNEL_BALANCE_EN : 1; /* 22:22 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_bpc_pdpc_module_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_MODULE_CFG;

typedef struct{
    unsigned  BLACK_LEVEL : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _bps_bps_0_clc_bpc_pdpc_pdpc_black_level;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdpc_black_level bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDPC_BLACK_LEVEL;

typedef struct{
    unsigned  EXP_RATIO_RECIP : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  EXP_RATIO : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_hdr_exp_ratio;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_hdr_exp_ratio bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_HDR_EXP_RATIO;

typedef struct{
    unsigned  FMIN_PIXEL_Q6 : 8; /* 7:0 */
    unsigned  FMAX_PIXEL_Q6 : 8; /* 15:8 */
    unsigned  CORRECTION_THRESHOLD : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_clc_bpc_pdpc_bad_pixel_thresholds;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_bad_pixel_thresholds bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_THRESHOLDS;

typedef struct{
    unsigned  BPC_OFFSET : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  BCC_OFFSET : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_bpc_pdpc_bad_pixel_det_offset;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_bad_pixel_det_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET;

typedef struct{
    unsigned  RG_WB_GAIN : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_rg_wb_gain;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_rg_wb_gain bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_RG_WB_GAIN;

typedef struct{
    unsigned  BG_WB_GAIN : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_bg_wb_gain;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_bg_wb_gain bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_BG_WB_GAIN;

typedef struct{
    unsigned  GR_WB_GAIN : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_gr_wb_gain;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_gr_wb_gain bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_GR_WB_GAIN;

typedef struct{
    unsigned  GB_WB_GAIN : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_gb_wb_gain;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_gb_wb_gain bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_GB_WB_GAIN;

typedef struct{
    unsigned  X_OFFSET : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  Y_OFFSET : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_loc_offset_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_loc_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_OFFSET_CFG;

typedef struct{
    unsigned  X_END : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  Y_END : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_loc_end_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_loc_end_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_LOC_END_CFG;

typedef struct{
    unsigned  PERIOD : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  BLK_OUT : 12; /* 15:4 */
    unsigned  UNUSED1 : 4; /* 19:16 */
    unsigned  BLK_IN : 12; /* 31:20 */
} _bps_bps_0_clc_bpc_pdpc_demux_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_CFG;

typedef struct{
    unsigned  CH0_GAIN_EVEN : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  CH0_GAIN_ODD : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_bpc_pdpc_demux_gain_ch0;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_gain_ch0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH0;

typedef struct{
    unsigned  CH1_GAIN : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  CH2_GAIN : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_bpc_pdpc_demux_gain_ch12;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_gain_ch12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_CH12;

typedef struct{
    unsigned  CH0_GAIN_EVEN : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  CH0_GAIN_ODD : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_bpc_pdpc_demux_gain_right_ch0;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_gain_right_ch0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH0;

typedef struct{
    unsigned  CH1_GAIN : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  CH2_GAIN : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_bpc_pdpc_demux_gain_right_ch12;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_gain_right_ch12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_GAIN_RIGHT_CH12;

typedef struct{
    unsigned  EVEN_LINE_PATTERN : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_demux_even_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_even_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_EVEN_CFG;

typedef struct{
    unsigned  ODD_LINE_PATTERN : 32; /* 31:0 */
} _bps_bps_0_clc_bpc_pdpc_demux_odd_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_demux_odd_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_DEMUX_ODD_CFG;

typedef struct{
    unsigned  BPC_OFFSET_T2 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  BCC_OFFSET_T2 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_bpc_pdpc_bad_pixel_det_offset_t2;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_bad_pixel_det_offset_t2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_BAD_PIXEL_DET_OFFSET_T2;

typedef struct{
    unsigned  SAT_THRESHOLD : 14; /* 13:0 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _bps_bps_0_clc_bpc_pdpc_saturation_threshold;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_saturation_threshold bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_SATURATION_THRESHOLD;

typedef struct{
    unsigned  X_OFFSET : 5; /* 4:0 */
    unsigned  UNUSED0 : 11; /* 15:5 */
    unsigned  Y_OFFSET : 6; /* 21:16 */
    unsigned  UNUSED1 : 10; /* 31:22 */
} _bps_bps_0_clc_bpc_pdpc_pdaf_tab_offset_cfg;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_pdaf_tab_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_PDAF_TAB_OFFSET_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_bpc_pdpc_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_bpc_pdpc_spare;

typedef union{
    _bps_bps_0_clc_bpc_pdpc_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_BPC_PDPC_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_hdr_recon_hw_version;

typedef union{
    _bps_bps_0_clc_hdr_recon_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hdr_recon_hw_status;

typedef union{
    _bps_bps_0_clc_hdr_recon_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_hdr_recon_module_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_MODULE_CFG;

typedef struct{
    unsigned  ZREC_ENABLE : 1; /* 0:0 */
    unsigned  RECON_LINEAR_MODE : 1; /* 1:1 */
    unsigned  EXP_RATIO : 15; /* 16:2 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_hdr_recon_hdr_0_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_hdr_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_HDR_0_CFG;

typedef struct{
    unsigned  RG_WB_GAIN_RATIO : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_hdr_recon_hdr_1_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_hdr_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_HDR_1_CFG;

typedef struct{
    unsigned  BG_WB_GAIN_RATIO : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_hdr_recon_hdr_2_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_hdr_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_HDR_2_CFG;

typedef struct{
    unsigned  BLK_IN : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _bps_bps_0_clc_hdr_recon_hdr_3_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_hdr_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_HDR_3_CFG;

typedef struct{
    unsigned  RECON_MOTION_DTH_LOG2 : 4; /* 3:0 */
    unsigned  UNUSED0 : 1; /* 4:4 */
    unsigned  RECON_MOTION_TH1 : 10; /* 14:5 */
    unsigned  UNUSED1 : 1; /* 15:15 */
    unsigned  RECON_H_EDGE_DTH_LOG2 : 4; /* 19:16 */
    unsigned  RECON_H_EDGE_TH1 : 10; /* 29:20 */
    unsigned  UNUSED2 : 2; /* 31:30 */
} _bps_bps_0_clc_hdr_recon_ihdr_0_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_ihdr_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_IHDR_0_CFG;

typedef struct{
    unsigned  RECON_EDGE_LPF_TAP0 : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  RECON_FLAT_REGION_TH : 10; /* 13:4 */
    unsigned  UNUSED1 : 1; /* 14:14 */
    unsigned  RECON_DARK_DTH_LOG2 : 3; /* 17:15 */
    unsigned  UNUSED2 : 1; /* 18:18 */
    unsigned  RECON_DARK_TH1 : 10; /* 28:19 */
    unsigned  UNUSED3 : 1; /* 29:29 */
    unsigned  RECON_FIRST_FIELD : 1; /* 30:30 */
    unsigned  UNUSED4 : 1; /* 31:31 */
} _bps_bps_0_clc_hdr_recon_ihdr_1_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_ihdr_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_IHDR_1_CFG;

typedef struct{
    unsigned  RECON_MIN_FACTOR : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_clc_hdr_recon_ihdr_2_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_ihdr_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_IHDR_2_CFG;

typedef struct{
    unsigned  ZREC_PREFILT_TAP0 : 7; /* 6:0 */
    unsigned  UNUSED0 : 1; /* 7:7 */
    unsigned  ZREC_PATTERN : 2; /* 9:8 */
    unsigned  UNUSED1 : 1; /* 10:10 */
    unsigned  ZREC_FIRST_RB_EXP : 1; /* 11:11 */
    unsigned  UNUSED2 : 20; /* 31:12 */
} _bps_bps_0_clc_hdr_recon_zhdr_0_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_zhdr_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_ZHDR_0_CFG;

typedef struct{
    unsigned  ZREC_RB_DTH_LOG2 : 4; /* 3:0 */
    unsigned  ZREC_RB_GRAD_TH1 : 12; /* 15:4 */
    unsigned  ZREC_G_DTH_LOG2 : 4; /* 19:16 */
    unsigned  ZREC_G_GRAD_TH1 : 12; /* 31:20 */
} _bps_bps_0_clc_hdr_recon_zhdr_1_cfg;

typedef union{
    _bps_bps_0_clc_hdr_recon_zhdr_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_ZHDR_1_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_hdr_recon_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_hdr_recon_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hdr_recon_spare;

typedef union{
    _bps_bps_0_clc_hdr_recon_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_RECON_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_hdr_mac_hw_version;

typedef union{
    _bps_bps_0_clc_hdr_mac_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hdr_mac_hw_status;

typedef union{
    _bps_bps_0_clc_hdr_mac_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_hdr_mac_module_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_MODULE_CFG;

typedef struct{
    unsigned  EXP_RATIO : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  EXP_RATIO_RECIP : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_0_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_0_CFG;

typedef struct{
    unsigned  GB_WB_GAIN_RATIO : 17; /* 16:0 */
    unsigned  UNUSED0 : 3; /* 19:17 */
    unsigned  BLK_IN : 8; /* 27:20 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_1_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_1_CFG;

typedef struct{
    unsigned  GR_WB_GAIN_RATIO : 17; /* 16:0 */
    unsigned  UNUSED0 : 3; /* 19:17 */
    unsigned  BLK_OUT : 12; /* 31:20 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_2_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_2_CFG;

typedef struct{
    unsigned  MAC_MOTION_0_TH1 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  MAC_MOTION_0_TH2 : 8; /* 23:16 */
    unsigned  MAC_SQRT_ANALOG_GAIN : 7; /* 30:24 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_3_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_3_CFG;

typedef struct{
    unsigned  MAC_DILATION : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  MAC_LOW_LIGHT_DTH_LOG2 : 4; /* 7:4 */
    unsigned  MAC_MOTION_0_DT0 : 6; /* 13:8 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  MAC_MOTION_STRENGTH : 5; /* 20:16 */
    unsigned  UNUSED2 : 3; /* 23:21 */
    unsigned  MAC_LOW_LIGHT_STRENGTH : 5; /* 28:24 */
    unsigned  UNUSED3 : 3; /* 31:29 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_4_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_4_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_4_CFG;

typedef struct{
    unsigned  MAC_LOW_LIGHT_TH1 : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  MAC_HIGH_LIGHT_TH1 : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_5_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_5_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_5_CFG;

typedef struct{
    unsigned  MAC_HIGH_LIGHT_DTH_LOG2 : 4; /* 3:0 */
    unsigned  MAC_SMOOTH_TH1 : 9; /* 12:4 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  MAC_SMOOTH_DTH_LOG2 : 4; /* 19:16 */
    unsigned  MAC_SMOOTH_TAP0 : 3; /* 22:20 */
    unsigned  UNUSED1 : 1; /* 23:23 */
    unsigned  MAC_SMOOTH_ENABLE : 1; /* 24:24 */
    unsigned  MSB_ALIGNED : 1; /* 25:25 */
    unsigned  MAC_LINEAR_MODE : 1; /* 26:26 */
    unsigned  UNUSED2 : 5; /* 31:27 */
} _bps_bps_0_clc_hdr_mac_hdr_mac_6_cfg;

typedef union{
    _bps_bps_0_clc_hdr_mac_hdr_mac_6_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_HDR_MAC_6_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_hdr_mac_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_hdr_mac_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hdr_mac_spare;

typedef union{
    _bps_bps_0_clc_hdr_mac_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HDR_MAC_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_gic_hw_version;

typedef union{
    _bps_bps_0_clc_gic_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gic_hw_status;

typedef union{
    _bps_bps_0_clc_gic_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_HW_STATUS;

typedef struct{
    unsigned  ADDR : 6; /* 5:0 */
    unsigned  UNUSED0 : 14; /* 19:6 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_gic_dmi_cfg;

typedef union{
    _bps_bps_0_clc_gic_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gic_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_gic_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data;

typedef union{
    _bps_bps_0_clc_gic_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_1;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_2;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_3;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_4;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_5;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_6;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_7;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_8;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_9;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_10;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_11;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_12;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_13;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_14;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gic_dmi_data_15;

typedef union{
    _bps_bps_0_clc_gic_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_gic_dmi_cmd;

typedef union{
    _bps_bps_0_clc_gic_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gic_dmi_status;

typedef union{
    _bps_bps_0_clc_gic_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gic_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_gic_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gic_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_gic_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 6; /* 7:2 */
    unsigned  PNR_EN : 1; /* 8:8 */
    unsigned  GIC_EN : 1; /* 9:9 */
    unsigned  UNUSED1 : 22; /* 31:10 */
} _bps_bps_0_clc_gic_module_cfg;

typedef union{
    _bps_bps_0_clc_gic_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_MODULE_CFG;

typedef struct{
    unsigned  GIC_FILTER_STRENGTH : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  GIC_NOISE_SCALE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_gic_filter_cfg;

typedef union{
    _bps_bps_0_clc_gic_gic_filter_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_GIC_FILTER_CFG;

typedef struct{
    unsigned  VALUE : 14; /* 13:0 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _bps_bps_0_clc_gic_thin_line_noise_offset;

typedef union{
    _bps_bps_0_clc_gic_thin_line_noise_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_THIN_LINE_NOISE_OFFSET;

typedef struct{
    unsigned  BASE_TABLE : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  ANCHOR_TABLE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_anchor_base_settings_0;

typedef union{
    _bps_bps_0_clc_gic_anchor_base_settings_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_0;

typedef struct{
    unsigned  BASE_TABLE : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  ANCHOR_TABLE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_anchor_base_settings_1;

typedef union{
    _bps_bps_0_clc_gic_anchor_base_settings_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_1;

typedef struct{
    unsigned  BASE_TABLE : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  ANCHOR_TABLE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_anchor_base_settings_2;

typedef union{
    _bps_bps_0_clc_gic_anchor_base_settings_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_2;

typedef struct{
    unsigned  BASE_TABLE : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  ANCHOR_TABLE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_anchor_base_settings_3;

typedef union{
    _bps_bps_0_clc_gic_anchor_base_settings_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_3;

typedef struct{
    unsigned  BASE_TABLE : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  ANCHOR_TABLE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_anchor_base_settings_4;

typedef union{
    _bps_bps_0_clc_gic_anchor_base_settings_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_4;

typedef struct{
    unsigned  BASE_TABLE : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  ANCHOR_TABLE : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_gic_anchor_base_settings_5;

typedef union{
    _bps_bps_0_clc_gic_anchor_base_settings_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_ANCHOR_BASE_SETTINGS_5;

typedef struct{
    unsigned  SHIFT_TABLE : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  SLOPE_TABLE : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_gic_slope_shift_settings_0;

typedef union{
    _bps_bps_0_clc_gic_slope_shift_settings_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_0;

typedef struct{
    unsigned  SHIFT_TABLE : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  SLOPE_TABLE : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_gic_slope_shift_settings_1;

typedef union{
    _bps_bps_0_clc_gic_slope_shift_settings_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_1;

typedef struct{
    unsigned  SHIFT_TABLE : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  SLOPE_TABLE : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_gic_slope_shift_settings_2;

typedef union{
    _bps_bps_0_clc_gic_slope_shift_settings_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_2;

typedef struct{
    unsigned  SHIFT_TABLE : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  SLOPE_TABLE : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_gic_slope_shift_settings_3;

typedef union{
    _bps_bps_0_clc_gic_slope_shift_settings_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_3;

typedef struct{
    unsigned  SHIFT_TABLE : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  SLOPE_TABLE : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_gic_slope_shift_settings_4;

typedef union{
    _bps_bps_0_clc_gic_slope_shift_settings_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_4;

typedef struct{
    unsigned  SHIFT_TABLE : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  SLOPE_TABLE : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_gic_slope_shift_settings_5;

typedef union{
    _bps_bps_0_clc_gic_slope_shift_settings_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SLOPE_SHIFT_SETTINGS_5;

typedef struct{
    unsigned  BY : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  BX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_gic_init_hv_offset;

typedef union{
    _bps_bps_0_clc_gic_init_hv_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_INIT_HV_OFFSET;

typedef struct{
    unsigned  VALUE : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _bps_bps_0_clc_gic_r_square_init;

typedef union{
    _bps_bps_0_clc_gic_r_square_init bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_R_SQUARE_INIT;

typedef struct{
    unsigned  R_SQUARE_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  R_SQUARE_SCALE : 7; /* 14:8 */
    unsigned  UNUSED1 : 17; /* 31:15 */
} _bps_bps_0_clc_gic_r_scale_shift;

typedef union{
    _bps_bps_0_clc_gic_r_scale_shift bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_R_SCALE_SHIFT;

typedef struct{
    unsigned  R_SQUARE_SCALE : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _bps_bps_0_clc_gic_pnr_noise_scale_0;

typedef union{
    _bps_bps_0_clc_gic_pnr_noise_scale_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_0;

typedef struct{
    unsigned  R_SQUARE_SCALE : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _bps_bps_0_clc_gic_pnr_noise_scale_1;

typedef union{
    _bps_bps_0_clc_gic_pnr_noise_scale_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_1;

typedef struct{
    unsigned  R_SQUARE_SCALE : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _bps_bps_0_clc_gic_pnr_noise_scale_2;

typedef union{
    _bps_bps_0_clc_gic_pnr_noise_scale_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_2;

typedef struct{
    unsigned  R_SQUARE_SCALE : 10; /* 9:0 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _bps_bps_0_clc_gic_pnr_noise_scale_3;

typedef union{
    _bps_bps_0_clc_gic_pnr_noise_scale_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_PNR_NOISE_SCALE_3;

typedef struct{
    unsigned  VALUE : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _bps_bps_0_clc_gic_pnr_filter_strength;

typedef union{
    _bps_bps_0_clc_gic_pnr_filter_strength bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_PNR_FILTER_STRENGTH;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gic_spare;

typedef union{
    _bps_bps_0_clc_gic_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GIC_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_abf_hw_version;

typedef union{
    _bps_bps_0_clc_abf_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_abf_hw_status;

typedef union{
    _bps_bps_0_clc_abf_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_HW_STATUS;

typedef struct{
    unsigned  ADDR : 8; /* 7:0 */
    unsigned  UNUSED0 : 12; /* 19:8 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_abf_dmi_cfg;

typedef union{
    _bps_bps_0_clc_abf_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_abf_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_abf_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data;

typedef union{
    _bps_bps_0_clc_abf_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_1;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_2;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_3;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_4;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_5;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_6;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_7;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_8;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_9;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_10;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_11;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_12;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_13;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_14;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_abf_dmi_data_15;

typedef union{
    _bps_bps_0_clc_abf_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_abf_dmi_cmd;

typedef union{
    _bps_bps_0_clc_abf_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_abf_dmi_status;

typedef union{
    _bps_bps_0_clc_abf_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_abf_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_abf_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_abf_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_abf_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 6; /* 7:2 */
    unsigned  FILTER_EN : 1; /* 8:8 */
    unsigned  ACT_ADJ_EN : 1; /* 9:9 */
    unsigned  DARK_SMOOTH_EN : 1; /* 10:10 */
    unsigned  DARK_DESAT_EN : 1; /* 11:11 */
    unsigned  DIR_SMOOTH_EN : 1; /* 12:12 */
    unsigned  MINMAX_EN : 1; /* 13:13 */
    unsigned  CROSS_PLANE_EN : 1; /* 14:14 */
    unsigned  BLS_EN : 1; /* 15:15 */
    unsigned  PIX_MATCH_LEVEL_RB : 3; /* 18:16 */
    unsigned  UNUSED1 : 1; /* 19:19 */
    unsigned  PIX_MATCH_LEVEL_G : 3; /* 22:20 */
    unsigned  UNUSED2 : 1; /* 23:23 */
    unsigned  BLOCK_MATCH_PATTERN_RB : 2; /* 25:24 */
    unsigned  UNUSED3 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_module_cfg;

typedef union{
    _bps_bps_0_clc_abf_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_MODULE_CFG;

typedef struct{
    unsigned  EDGE_SOFTNESS_GR : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  EDGE_SOFTNESS_GB : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_0_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_0_CFG;

typedef struct{
    unsigned  EDGE_SOFTNESS_R : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  EDGE_SOFTNESS_B : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_1_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_1_CFG;

typedef struct{
    unsigned  DISTANCE_LEVEL0_GRGB_0 : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  DISTANCE_LEVEL0_GRGB_1 : 2; /* 5:4 */
    unsigned  DISTANCE_LEVEL0_GRGB_2 : 1; /* 6:6 */
    unsigned  UNUSED1 : 1; /* 7:7 */
    unsigned  DISTANCE_LEVEL1_GRGB_0 : 3; /* 10:8 */
    unsigned  UNUSED2 : 1; /* 11:11 */
    unsigned  DISTANCE_LEVEL1_GRGB_1 : 2; /* 13:12 */
    unsigned  DISTANCE_LEVEL1_GRGB_2 : 1; /* 14:14 */
    unsigned  UNUSED3 : 1; /* 15:15 */
    unsigned  DISTANCE_LEVEL2_GRGB_0 : 3; /* 18:16 */
    unsigned  UNUSED4 : 1; /* 19:19 */
    unsigned  DISTANCE_LEVEL2_GRGB_1 : 2; /* 21:20 */
    unsigned  DISTANCE_LEVEL2_GRGB_2 : 1; /* 22:22 */
    unsigned  UNUSED5 : 9; /* 31:23 */
} _bps_bps_0_clc_abf_abf_2_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_2_CFG;

typedef struct{
    unsigned  DISTANCE_LEVEL0_RB_0 : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  DISTANCE_LEVEL0_RB_1 : 2; /* 5:4 */
    unsigned  DISTANCE_LEVEL0_RB_2 : 1; /* 6:6 */
    unsigned  UNUSED1 : 1; /* 7:7 */
    unsigned  DISTANCE_LEVEL1_RB_0 : 3; /* 10:8 */
    unsigned  UNUSED2 : 1; /* 11:11 */
    unsigned  DISTANCE_LEVEL1_RB_1 : 2; /* 13:12 */
    unsigned  DISTANCE_LEVEL1_RB_2 : 1; /* 14:14 */
    unsigned  UNUSED3 : 1; /* 15:15 */
    unsigned  DISTANCE_LEVEL2_RB_0 : 3; /* 18:16 */
    unsigned  UNUSED4 : 1; /* 19:19 */
    unsigned  DISTANCE_LEVEL2_RB_1 : 2; /* 21:20 */
    unsigned  DISTANCE_LEVEL2_RB_2 : 1; /* 22:22 */
    unsigned  UNUSED5 : 9; /* 31:23 */
} _bps_bps_0_clc_abf_abf_3_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_3_CFG;

typedef struct{
    unsigned  CURVE_OFFSET_GR : 7; /* 6:0 */
    unsigned  UNUSED0 : 1; /* 7:7 */
    unsigned  CURVE_OFFSET_R : 7; /* 14:8 */
    unsigned  UNUSED1 : 1; /* 15:15 */
    unsigned  CURVE_OFFSET_B : 7; /* 22:16 */
    unsigned  UNUSED2 : 1; /* 23:23 */
    unsigned  CURVE_OFFSET_GB : 7; /* 30:24 */
    unsigned  UNUSED3 : 1; /* 31:31 */
} _bps_bps_0_clc_abf_abf_4_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_4_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_4_CFG;

typedef struct{
    unsigned  FILTER_STRENGTH_GR : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  FILTER_STRENGTH_R : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_5_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_5_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_5_CFG;

typedef struct{
    unsigned  FILTER_STRENGTH_GB : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  FILTER_STRENGTH_B : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_6_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_6_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_6_CFG;

typedef struct{
    unsigned  MINMAX_MAX_SHIFT : 4; /* 3:0 */
    unsigned  MINMAX_OFFSET : 12; /* 15:4 */
    unsigned  MINMAX_MIN_SHIFT : 4; /* 19:16 */
    unsigned  MINMAX_BLS : 12; /* 31:20 */
} _bps_bps_0_clc_abf_abf_7_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_7_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_7_CFG;

typedef struct{
    unsigned  RNR_BX : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  RNR_BY : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_abf_abf_8_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_8_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_8_CFG;

typedef struct{
    unsigned  RNR_INIT_RSQUARE : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_9_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_9_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_9_CFG;

typedef struct{
    unsigned  RNR_RSQUARE_SHIFT : 4; /* 3:0 */
    unsigned  RNR_RSQUARE_SCALE : 7; /* 10:4 */
    unsigned  UNUSED0 : 21; /* 31:11 */
} _bps_bps_0_clc_abf_abf_10_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_10_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_10_CFG;

typedef struct{
    unsigned  RNR_ANCHOR_0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RNR_ANCHOR_1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_11_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_11_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_11_CFG;

typedef struct{
    unsigned  RNR_ANCHOR_2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RNR_ANCHOR_3 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_12_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_12_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_12_CFG;

typedef struct{
    unsigned  RNR_NOISE_BASE_0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RNR_NOISE_BASE_1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_13_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_13_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_13_CFG;

typedef struct{
    unsigned  RNR_NOISE_BASE_2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RNR_NOISE_BASE_3 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_14_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_14_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_14_CFG;

typedef struct{
    unsigned  RNR_NOISE_SLOPE_0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RNR_NOISE_SLOPE_1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_15_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_15_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_15_CFG;

typedef struct{
    unsigned  RNR_NOISE_SLOPE_2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RNR_NOISE_SLOPE_3 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_16_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_16_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_16_CFG;

typedef struct{
    unsigned  RNR_NOISE_SHIFT_0 : 4; /* 3:0 */
    unsigned  RNR_NOISE_SHIFT_1 : 4; /* 7:4 */
    unsigned  RNR_NOISE_SHIFT_2 : 4; /* 11:8 */
    unsigned  RNR_NOISE_SHIFT_3 : 4; /* 15:12 */
    unsigned  RNR_THRESH_SHIFT_0 : 4; /* 19:16 */
    unsigned  RNR_THRESH_SHIFT_1 : 4; /* 23:20 */
    unsigned  RNR_THRESH_SHIFT_2 : 4; /* 27:24 */
    unsigned  RNR_THRESH_SHIFT_3 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_17_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_17_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_17_CFG;

typedef struct{
    unsigned  RNR_THRESH_BASE_0 : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  RNR_THRESH_BASE_1 : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_18_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_18_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_18_CFG;

typedef struct{
    unsigned  RNR_THRESH_BASE_2 : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  RNR_THRESH_BASE_3 : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_19_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_19_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_19_CFG;

typedef struct{
    unsigned  RNR_THRESH_SLOPE_0 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_THRESH_SLOPE_1 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_abf_20_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_20_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_20_CFG;

typedef struct{
    unsigned  RNR_THRESH_SLOPE_2 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_THRESH_SLOPE_3 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_abf_21_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_21_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_21_CFG;

typedef struct{
    unsigned  NP_ANCHOR_0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  NP_ANCHOR_1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_22_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_22_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_22_CFG;

typedef struct{
    unsigned  NP_ANCHOR_2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  NP_ANCHOR_3 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_23_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_23_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_23_CFG;

typedef struct{
    unsigned  NP_BASE_RB_0 : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  NP_BASE_RB_1 : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_24_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_24_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_24_CFG;

typedef struct{
    unsigned  NP_BASE_RB_2 : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  NP_BASE_RB_3 : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_25_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_25_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_25_CFG;

typedef struct{
    unsigned  NP_SLOPE_RB_0 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  NP_SLOPE_RB_1 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_abf_26_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_26_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_26_CFG;

typedef struct{
    unsigned  NP_SLOPE_RB_2 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  NP_SLOPE_RB_3 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_abf_27_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_27_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_27_CFG;

typedef struct{
    unsigned  NP_SHIFT_RB_0 : 4; /* 3:0 */
    unsigned  NP_SHIFT_RB_1 : 4; /* 7:4 */
    unsigned  NP_SHIFT_RB_2 : 4; /* 11:8 */
    unsigned  NP_SHIFT_RB_3 : 4; /* 15:12 */
    unsigned  NP_SHIFT_GRGB_0 : 4; /* 19:16 */
    unsigned  NP_SHIFT_GRGB_1 : 4; /* 23:20 */
    unsigned  NP_SHIFT_GRGB_2 : 4; /* 27:24 */
    unsigned  NP_SHIFT_GRGB_3 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_28_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_28_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_28_CFG;

typedef struct{
    unsigned  NP_BASE_GRGB_0 : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  NP_BASE_GRGB_1 : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_29_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_29_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_29_CFG;

typedef struct{
    unsigned  NP_BASE_GRGB_2 : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  NP_BASE_GRGB_3 : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_abf_abf_30_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_30_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_30_CFG;

typedef struct{
    unsigned  NP_SLOPE_GRGB_0 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  NP_SLOPE_GRGB_1 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_abf_31_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_31_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_31_CFG;

typedef struct{
    unsigned  NP_SLOPE_GRGB_2 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  NP_SLOPE_GRGB_3 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_abf_abf_32_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_32_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_32_CFG;

typedef struct{
    unsigned  ACT_FAC0 : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  ACT_FAC1 : 13; /* 28:16 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_abf_abf_33_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_33_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_33_CFG;

typedef struct{
    unsigned  ACT_THD0 : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  ACT_THD1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_34_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_34_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_34_CFG;

typedef struct{
    unsigned  ACT_SMOOTH_THD0 : 8; /* 7:0 */
    unsigned  ACT_SMOOTH_THD1 : 8; /* 15:8 */
    unsigned  DARK_THD : 12; /* 27:16 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_35_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_35_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_35_CFG;

typedef struct{
    unsigned  GR_RATIO : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RG_RATIO : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_36_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_36_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_36_CFG;

typedef struct{
    unsigned  GB_RATIO : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  BG_RATIO : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_37_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_37_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_37_CFG;

typedef struct{
    unsigned  RB_RATIO : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  BR_RATIO : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_38_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_38_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_38_CFG;

typedef struct{
    unsigned  EDGE_DETECT_THD : 4; /* 3:0 */
    unsigned  EDGE_DETECT_NOISE_SCALAR : 12; /* 15:4 */
    unsigned  EDGE_COUNT_THD : 5; /* 20:16 */
    unsigned  UNUSED0 : 3; /* 23:21 */
    unsigned  EDGE_SMOOTH_STRENGTH : 7; /* 30:24 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_abf_abf_39_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_39_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_39_CFG;

typedef struct{
    unsigned  EDGE_SMOOTH_NOISE_SCALAR_GR : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  EDGE_SMOOTH_NOISE_SCALAR_R : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_40_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_40_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_40_CFG;

typedef struct{
    unsigned  EDGE_SMOOTH_NOISE_SCALAR_GB : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  EDGE_SMOOTH_NOISE_SCALAR_B : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_abf_abf_41_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_41_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_41_CFG;

typedef struct{
    unsigned  BLS_THRESH_GR : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  BLS_THRESH_R : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_abf_abf_42_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_42_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_42_CFG;

typedef struct{
    unsigned  BLS_THRESH_GB : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  BLS_THRESH_B : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_abf_abf_43_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_43_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_43_CFG;

typedef struct{
    unsigned  BLS_OFFSET : 14; /* 13:0 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _bps_bps_0_clc_abf_abf_44_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_44_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_44_CFG;

typedef struct{
    unsigned  BLS_SCALE : 17; /* 16:0 */
    unsigned  UNUSED0 : 15; /* 31:17 */
} _bps_bps_0_clc_abf_abf_45_cfg;

typedef union{
    _bps_bps_0_clc_abf_abf_45_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_ABF_45_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_abf_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_abf_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_abf_spare;

typedef union{
    _bps_bps_0_clc_abf_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_ABF_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  CH0_CLAMP_MAX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  CH1_CLAMP_MAX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  CH2_CLAMP_MAX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_bayer_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_bayer_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_BAYER_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_lens_rolloff_hw_version;

typedef union{
    _bps_bps_0_clc_lens_rolloff_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_lens_rolloff_hw_status;

typedef union{
    _bps_bps_0_clc_lens_rolloff_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_HW_STATUS;

typedef struct{
    unsigned  ADDR : 8; /* 7:0 */
    unsigned  UNUSED0 : 12; /* 19:8 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_lens_rolloff_dmi_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_lens_rolloff_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_1;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_2;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_3;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_4;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_5;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_6;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_7;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_8;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_9;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_10;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_11;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_12;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_13;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_14;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_lens_rolloff_dmi_data_15;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_lens_rolloff_dmi_cmd;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_lens_rolloff_dmi_status;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_lens_rolloff_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_lens_rolloff_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 11; /* 11:1 */
    unsigned  NUM_SUBBLOCKS : 2; /* 13:12 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  INIT_BLOCK_X : 4; /* 19:16 */
    unsigned  INIT_BLOCK_Y : 4; /* 23:20 */
    unsigned  INIT_SUBBLOCK_X : 3; /* 26:24 */
    unsigned  UNUSED2 : 1; /* 27:27 */
    unsigned  INIT_SUBBLOCK_Y : 3; /* 30:28 */
    unsigned  UNUSED3 : 1; /* 31:31 */
} _bps_bps_0_clc_lens_rolloff_module_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_CFG;

typedef struct{
    unsigned  NUM_BLOCKS_X : 4; /* 3:0 */
    unsigned  NUM_BLOCKS_Y : 4; /* 7:4 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_0_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_0_CFG;

typedef struct{
    unsigned  BLOCK_WIDTH : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  BLOCK_HEIGHT : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_1_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_1_CFG;

typedef struct{
    unsigned  SUBBLOCK_WIDTH : 11; /* 10:0 */
    unsigned  UNUSED0 : 1; /* 11:11 */
    unsigned  INV_SUBBLOCK_WIDTH : 17; /* 28:12 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_2_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_2_CFG;

typedef struct{
    unsigned  SUBBLOCK_HEIGHT : 10; /* 9:0 */
    unsigned  UNUSED0 : 2; /* 11:10 */
    unsigned  INV_SUBBLOCK_HEIGHT : 17; /* 28:12 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_3_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_3_CFG;

typedef struct{
    unsigned  INIT_PIXEL_X : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  INIT_PIXEL_Y : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_4_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_4_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_4_CFG;

typedef struct{
    unsigned  PIXEL_OFFSET : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_5_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_5_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_5_CFG;

typedef struct{
    unsigned  INIT_YDELTA : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _bps_bps_0_clc_lens_rolloff_lens_rolloff_6_cfg;

typedef union{
    _bps_bps_0_clc_lens_rolloff_lens_rolloff_6_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_LENS_ROLLOFF_6_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_lens_rolloff_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_lens_rolloff_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_lens_rolloff_spare;

typedef union{
    _bps_bps_0_clc_lens_rolloff_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_LENS_ROLLOFF_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_demosaic_hw_version;

typedef union{
    _bps_bps_0_clc_demosaic_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_demosaic_hw_status;

typedef union{
    _bps_bps_0_clc_demosaic_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 8; /* 9:2 */
    unsigned  COSITED_RGB_EN : 1; /* 10:10 */
    unsigned  UNUSED1 : 1; /* 11:11 */
    unsigned  DIR_G_INTERP_DIS : 1; /* 12:12 */
    unsigned  DIR_RB_INTERP_DIS : 1; /* 13:13 */
    unsigned  DYN_G_CLAMP_EN : 1; /* 14:14 */
    unsigned  DYN_RB_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED2 : 16; /* 31:16 */
} _bps_bps_0_clc_demosaic_module_cfg;

typedef union{
    _bps_bps_0_clc_demosaic_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_MODULE_CFG;

typedef struct{
    unsigned  G_GAIN : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  B_GAIN : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_demosaic_wb_gain_cfg_0;

typedef union{
    _bps_bps_0_clc_demosaic_wb_gain_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_0;

typedef struct{
    unsigned  R_GAIN : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _bps_bps_0_clc_demosaic_wb_gain_cfg_1;

typedef union{
    _bps_bps_0_clc_demosaic_wb_gain_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_WB_GAIN_CFG_1;

typedef struct{
    unsigned  G_OFFSET : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  B_OFFSET : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _bps_bps_0_clc_demosaic_wb_offset_cfg_0;

typedef union{
    _bps_bps_0_clc_demosaic_wb_offset_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_0;

typedef struct{
    unsigned  R_OFFSET : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _bps_bps_0_clc_demosaic_wb_offset_cfg_1;

typedef union{
    _bps_bps_0_clc_demosaic_wb_offset_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_WB_OFFSET_CFG_1;

typedef struct{
    unsigned  LAMDA_G : 8; /* 7:0 */
    unsigned  UNUSED0 : 8; /* 15:8 */
    unsigned  LAMDA_RB : 8; /* 23:16 */
    unsigned  UNUSED1 : 8; /* 31:24 */
} _bps_bps_0_clc_demosaic_interp_coeff_cfg;

typedef union{
    _bps_bps_0_clc_demosaic_interp_coeff_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_INTERP_COEFF_CFG;

typedef struct{
    unsigned  W_K : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  A_K : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_demosaic_interp_classifier_cfg;

typedef union{
    _bps_bps_0_clc_demosaic_interp_classifier_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_INTERP_CLASSIFIER_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_demosaic_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_demosaic_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_demosaic_spare;

typedef union{
    _bps_bps_0_clc_demosaic_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DEMOSAIC_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_stats_bg_hw_version;

typedef union{
    _bps_bps_0_clc_stats_bg_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  OVERFLOW_ERROR : 1; /* 1:1 */
    unsigned  OVERWRITE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_stats_bg_hw_status;

typedef union{
    _bps_bps_0_clc_stats_bg_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  SAT_STATS_EN : 1; /* 8:8 */
    unsigned  QUAD_SYNC_EN : 1; /* 9:9 */
    unsigned  SHIFT_BITS : 3; /* 12:10 */
    unsigned  UNUSED1 : 3; /* 15:13 */
    unsigned  RGN_SAMPLE_PATTERN : 16; /* 31:16 */
} _bps_bps_0_clc_stats_bg_module_cfg;

typedef union{
    _bps_bps_0_clc_stats_bg_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_MODULE_CFG;

typedef struct{
    unsigned  Y_STATS_EN : 1; /* 0:0 */
    unsigned  G_SEL : 2; /* 2:1 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  COEF_A0 : 8; /* 11:4 */
    unsigned  UNUSED1 : 1; /* 12:12 */
    unsigned  COEF_A1 : 8; /* 20:13 */
    unsigned  UNUSED2 : 1; /* 21:21 */
    unsigned  COEF_A2 : 8; /* 29:22 */
    unsigned  UNUSED3 : 2; /* 31:30 */
} _bps_bps_0_clc_stats_bg_ch_y_cfg;

typedef union{
    _bps_bps_0_clc_stats_bg_ch_y_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_CH_Y_CFG;

typedef struct{
    unsigned  RGN_H_OFFSET : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  RGN_H_NUM : 7; /* 22:16 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_stats_bg_horz_rgn_cfg_0;

typedef union{
    _bps_bps_0_clc_stats_bg_horz_rgn_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_0;

typedef struct{
    unsigned  RGN_WIDTH : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _bps_bps_0_clc_stats_bg_horz_rgn_cfg_1;

typedef union{
    _bps_bps_0_clc_stats_bg_horz_rgn_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_HORZ_RGN_CFG_1;

typedef struct{
    unsigned  RGN_V_OFFSET : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  RGN_V_NUM : 7; /* 22:16 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_stats_bg_vert_rgn_cfg_0;

typedef union{
    _bps_bps_0_clc_stats_bg_vert_rgn_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_0;

typedef struct{
    unsigned  RGN_HEIGHT : 9; /* 8:0 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _bps_bps_0_clc_stats_bg_vert_rgn_cfg_1;

typedef union{
    _bps_bps_0_clc_stats_bg_vert_rgn_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_VERT_RGN_CFG_1;

typedef struct{
    unsigned  FIRST_RGN_WIDTH : 9; /* 8:0 */
    unsigned  UNUSED0 : 7; /* 15:9 */
    unsigned  LAST_RGN_WIDTH : 9; /* 24:16 */
    unsigned  UNUSED1 : 7; /* 31:25 */
} _bps_bps_0_clc_stats_bg_rgn_width_cfg;

typedef union{
    _bps_bps_0_clc_stats_bg_rgn_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_RGN_WIDTH_CFG;

typedef struct{
    unsigned  R_MAX : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  GR_MAX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_stats_bg_hi_threshold_cfg_0;

typedef union{
    _bps_bps_0_clc_stats_bg_hi_threshold_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_0;

typedef struct{
    unsigned  B_MAX : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  GB_MAX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_stats_bg_hi_threshold_cfg_1;

typedef union{
    _bps_bps_0_clc_stats_bg_hi_threshold_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_HI_THRESHOLD_CFG_1;

typedef struct{
    unsigned  R_MIN : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  GR_MIN : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_stats_bg_lo_threshold_cfg_0;

typedef union{
    _bps_bps_0_clc_stats_bg_lo_threshold_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_0;

typedef struct{
    unsigned  B_MIN : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  GB_MIN : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_stats_bg_lo_threshold_cfg_1;

typedef union{
    _bps_bps_0_clc_stats_bg_lo_threshold_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_LO_THRESHOLD_CFG_1;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_stats_bg_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_stats_bg_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_stats_bg_spare;

typedef union{
    _bps_bps_0_clc_stats_bg_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_BG_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_stats_hdr_bhist_hw_version;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  OVERWRITE : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_stats_hdr_bhist_hw_status;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_HW_STATUS;

typedef struct{
    unsigned  ADDR : 8; /* 7:0 */
    unsigned  UNUSED0 : 12; /* 19:8 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_1;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_2;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_3;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_4;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_5;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_6;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_7;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_8;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_9;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_10;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_11;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_12;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_13;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_14;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_data_15;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_cmd;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_status;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_stats_hdr_bhist_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_stats_hdr_bhist_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  HDR_BHIST_CHAN_SEL : 1; /* 8:8 */
    unsigned  HDR_BHIST_FIELD_SEL : 2; /* 10:9 */
    unsigned  HDR_BHIST_SITE_SEL : 1; /* 11:11 */
    unsigned  UNUSED1 : 20; /* 31:12 */
} _bps_bps_0_clc_stats_hdr_bhist_module_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_CFG;

typedef struct{
    unsigned  RGN_H_OFFSET : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  RGN_V_OFFSET : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_stats_hdr_bhist_rgn_offset_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_rgn_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_OFFSET_CFG;

typedef struct{
    unsigned  RGN_H_NUM : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  RGN_V_NUM : 13; /* 28:16 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_stats_hdr_bhist_rgn_num_cfg;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_rgn_num_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_RGN_NUM_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_stats_hdr_bhist_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_stats_hdr_bhist_spare;

typedef union{
    _bps_bps_0_clc_stats_hdr_bhist_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_STATS_HDR_BHIST_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_color_correct_hw_version;

typedef union{
    _bps_bps_0_clc_color_correct_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_color_correct_hw_status;

typedef union{
    _bps_bps_0_clc_color_correct_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_color_correct_module_cfg;

typedef union{
    _bps_bps_0_clc_color_correct_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_MODULE_CFG;

typedef struct{
    unsigned  MATRIX_A0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  MATRIX_A1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_color_correct_color_correct_coeff_a_cfg_0;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_coeff_a_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_0;

typedef struct{
    unsigned  MATRIX_A2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _bps_bps_0_clc_color_correct_color_correct_coeff_a_cfg_1;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_coeff_a_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_A_CFG_1;

typedef struct{
    unsigned  MATRIX_B0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  MATRIX_B1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_color_correct_color_correct_coeff_b_cfg_0;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_coeff_b_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_0;

typedef struct{
    unsigned  MATRIX_B2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _bps_bps_0_clc_color_correct_color_correct_coeff_b_cfg_1;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_coeff_b_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_B_CFG_1;

typedef struct{
    unsigned  MATRIX_C0 : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  MATRIX_C1 : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _bps_bps_0_clc_color_correct_color_correct_coeff_c_cfg_0;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_coeff_c_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_0;

typedef struct{
    unsigned  MATRIX_C2 : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _bps_bps_0_clc_color_correct_color_correct_coeff_c_cfg_1;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_coeff_c_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_COEFF_C_CFG_1;

typedef struct{
    unsigned  OFFSET_K0 : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  OFFSET_K1 : 13; /* 28:16 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_color_correct_color_correct_offset_k_cfg_0;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_offset_k_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_0;

typedef struct{
    unsigned  OFFSET_K2 : 13; /* 12:0 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _bps_bps_0_clc_color_correct_color_correct_offset_k_cfg_1;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_offset_k_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_OFFSET_K_CFG_1;

typedef struct{
    unsigned  M_PARAM : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_color_correct_color_correct_shift_m_cfg;

typedef union{
    _bps_bps_0_clc_color_correct_color_correct_shift_m_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_COLOR_CORRECT_SHIFT_M_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_color_correct_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_color_correct_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_color_correct_spare;

typedef union{
    _bps_bps_0_clc_color_correct_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_CORRECT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_gtm_hw_version;

typedef union{
    _bps_bps_0_clc_gtm_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_hw_status;

typedef union{
    _bps_bps_0_clc_gtm_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_HW_STATUS;

typedef struct{
    unsigned  ADDR : 6; /* 5:0 */
    unsigned  UNUSED0 : 14; /* 19:6 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_gtm_dmi_cfg;

typedef union{
    _bps_bps_0_clc_gtm_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_gtm_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_1;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_2;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_3;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_4;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_5;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_6;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_7;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_8;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_9;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_10;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_11;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_12;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_13;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_14;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_gtm_dmi_data_15;

typedef union{
    _bps_bps_0_clc_gtm_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_gtm_dmi_cmd;

typedef union{
    _bps_bps_0_clc_gtm_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_dmi_status;

typedef union{
    _bps_bps_0_clc_gtm_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_gtm_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_gtm_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_module_cfg;

typedef union{
    _bps_bps_0_clc_gtm_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_MODULE_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_gtm_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_gtm_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_gtm_spare;

typedef union{
    _bps_bps_0_clc_gtm_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GTM_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_glut_hw_version;

typedef union{
    _bps_bps_0_clc_glut_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_glut_hw_status;

typedef union{
    _bps_bps_0_clc_glut_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_HW_STATUS;

typedef struct{
    unsigned  ADDR : 6; /* 5:0 */
    unsigned  UNUSED0 : 14; /* 19:6 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_glut_dmi_cfg;

typedef union{
    _bps_bps_0_clc_glut_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_glut_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_glut_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data;

typedef union{
    _bps_bps_0_clc_glut_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_1;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_2;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_3;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_4;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_5;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_6;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_7;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_8;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_9;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_10;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_11;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_12;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_13;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_14;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_glut_dmi_data_15;

typedef union{
    _bps_bps_0_clc_glut_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_glut_dmi_cmd;

typedef union{
    _bps_bps_0_clc_glut_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_glut_dmi_status;

typedef union{
    _bps_bps_0_clc_glut_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_glut_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_glut_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_glut_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_glut_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_glut_module_cfg;

typedef union{
    _bps_bps_0_clc_glut_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_MODULE_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_glut_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_glut_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_glut_spare;

typedef union{
    _bps_bps_0_clc_glut_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_GLUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_color_xform_hw_version;

typedef union{
    _bps_bps_0_clc_color_xform_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_color_xform_hw_status;

typedef union{
    _bps_bps_0_clc_color_xform_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_color_xform_module_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_MODULE_CFG;

typedef struct{
    unsigned  MATRIX_M00 : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  MATRIX_M01 : 13; /* 28:16 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_color_xform_color_xform_ch0_coeff_cfg_0;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch0_coeff_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_0;

typedef struct{
    unsigned  MATRIX_M02 : 13; /* 12:0 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _bps_bps_0_clc_color_xform_color_xform_ch0_coeff_cfg_1;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch0_coeff_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_COEFF_CFG_1;

typedef struct{
    unsigned  OFFSET_S0 : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  OFFSET_O0 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_color_xform_color_xform_ch0_offset_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch0_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_OFFSET_CFG;

typedef struct{
    unsigned  CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_color_xform_color_xform_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH0_CLAMP_CFG;

typedef struct{
    unsigned  MATRIX_M10 : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  MATRIX_M11 : 13; /* 28:16 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_color_xform_color_xform_ch1_coeff_cfg_0;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch1_coeff_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_0;

typedef struct{
    unsigned  MATRIX_M12 : 13; /* 12:0 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _bps_bps_0_clc_color_xform_color_xform_ch1_coeff_cfg_1;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch1_coeff_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_COEFF_CFG_1;

typedef struct{
    unsigned  OFFSET_S1 : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  OFFSET_O1 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_color_xform_color_xform_ch1_offset_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch1_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_OFFSET_CFG;

typedef struct{
    unsigned  CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_color_xform_color_xform_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH1_CLAMP_CFG;

typedef struct{
    unsigned  MATRIX_M20 : 13; /* 12:0 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  MATRIX_M21 : 13; /* 28:16 */
    unsigned  UNUSED1 : 3; /* 31:29 */
} _bps_bps_0_clc_color_xform_color_xform_ch2_coeff_cfg_0;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch2_coeff_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_0;

typedef struct{
    unsigned  MATRIX_M22 : 13; /* 12:0 */
    unsigned  UNUSED0 : 19; /* 31:13 */
} _bps_bps_0_clc_color_xform_color_xform_ch2_coeff_cfg_1;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch2_coeff_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_COEFF_CFG_1;

typedef struct{
    unsigned  OFFSET_S2 : 11; /* 10:0 */
    unsigned  UNUSED0 : 5; /* 15:11 */
    unsigned  OFFSET_O2 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_color_xform_color_xform_ch2_offset_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch2_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_OFFSET_CFG;

typedef struct{
    unsigned  CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_color_xform_color_xform_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_color_xform_color_xform_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_COLOR_XFORM_CH2_CLAMP_CFG;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_color_xform_spare;

typedef union{
    _bps_bps_0_clc_color_xform_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_COLOR_XFORM_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_y_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_y_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_Y_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_yuv_c_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_yuv_c_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_YUV_C_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_chroma_subsample_hw_version;

typedef union{
    _bps_bps_0_clc_chroma_subsample_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  OVERFLOW_ERROR : 1; /* 1:1 */
    unsigned  OVERWRITE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_chroma_subsample_hw_status;

typedef union{
    _bps_bps_0_clc_chroma_subsample_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_chroma_subsample_module_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_MODULE_CFG;

typedef struct{
    unsigned  UNUSED0 : 9; /* 8:0 */
    unsigned  HORIZONTAL_SCALE_EN : 1; /* 9:9 */
    unsigned  VERTICAL_SCALE_EN : 1; /* 10:10 */
    unsigned  UNUSED1 : 1; /* 11:11 */
    unsigned  HORIZONTAL_ROUNDING : 2; /* 13:12 */
    unsigned  UNUSED2 : 1; /* 14:14 */
    unsigned  VERTICAL_ROUNDING : 2; /* 16:15 */
    unsigned  UNUSED3 : 1; /* 17:17 */
    unsigned  HORIZONTAL_TERMINATION_EN : 1; /* 18:18 */
    unsigned  VERTICAL_TERMINATION_EN : 1; /* 19:19 */
    unsigned  UNUSED4 : 12; /* 31:20 */
} _bps_bps_0_clc_chroma_subsample_downscale_mn_c_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_downscale_mn_c_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_CFG;

typedef struct{
    unsigned  INPUT_HEIGHT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  INPUT_WIDTH : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_chroma_subsample_downscale_mn_c_image_size_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_downscale_mn_c_image_size_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_IMAGE_SIZE_CFG;

typedef struct{
    unsigned  PHASE_STEP_H : 29; /* 28:0 */
    unsigned  UNUSED0 : 1; /* 29:29 */
    unsigned  H_INTERP_RESO : 2; /* 31:30 */
} _bps_bps_0_clc_chroma_subsample_downscale_mn_c_h_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_downscale_mn_c_h_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_CFG;

typedef struct{
    unsigned  PHASE_INIT_H : 29; /* 28:0 */
    unsigned  UNUSED0 : 3; /* 31:29 */
} _bps_bps_0_clc_chroma_subsample_downscale_mn_c_h_phase_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_downscale_mn_c_h_phase_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_H_PHASE_CFG;

typedef struct{
    unsigned  PHASE_STEP_V : 29; /* 28:0 */
    unsigned  UNUSED0 : 1; /* 29:29 */
    unsigned  V_INTERP_RESO : 2; /* 31:30 */
} _bps_bps_0_clc_chroma_subsample_downscale_mn_c_v_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_downscale_mn_c_v_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_CFG;

typedef struct{
    unsigned  PHASE_INIT_V : 29; /* 28:0 */
    unsigned  UNUSED0 : 3; /* 31:29 */
} _bps_bps_0_clc_chroma_subsample_downscale_mn_c_v_phase_cfg;

typedef union{
    _bps_bps_0_clc_chroma_subsample_downscale_mn_c_v_phase_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_DOWNSCALE_MN_C_V_PHASE_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_chroma_subsample_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_chroma_subsample_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_chroma_subsample_spare;

typedef union{
    _bps_bps_0_clc_chroma_subsample_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CHROMA_SUBSAMPLE_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_hw_version;

typedef union{
    _bps_bps_0_clc_hnr_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hnr_hw_status;

typedef union{
    _bps_bps_0_clc_hnr_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_HW_STATUS;

typedef struct{
    unsigned  ADDR : 9; /* 8:0 */
    unsigned  UNUSED0 : 11; /* 19:9 */
    unsigned  AUTO_LOAD_EN : 1; /* 20:20 */
    unsigned  AUTO_LOAD_PATTERN : 2; /* 22:21 */
    unsigned  UNUSED1 : 9; /* 31:23 */
} _bps_bps_0_clc_hnr_dmi_cfg;

typedef union{
    _bps_bps_0_clc_hnr_dmi_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_CFG;

typedef struct{
    unsigned  LUT_SEL : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_hnr_dmi_lut_cfg;

typedef union{
    _bps_bps_0_clc_hnr_dmi_lut_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_LUT_CFG;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_1;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_1;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_2;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_2;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_3;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_3;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_4;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_4;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_5;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_5;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_6;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_6;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_7;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_7;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_8;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_8;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_9;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_9 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_9;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_10;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_10 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_10;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_11;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_11 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_11;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_12;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_12 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_12;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_13;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_13 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_13;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_14;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_14 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_14;

typedef struct{
    unsigned  DATA : 32; /* 31:0 */
} _bps_bps_0_clc_hnr_dmi_data_15;

typedef union{
    _bps_bps_0_clc_hnr_dmi_data_15 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_DATA_15;

typedef struct{
    unsigned  AUTO_LOAD_CMD : 1; /* 0:0 */
    unsigned  AUTO_LOAD_STATUS_CLR : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_clc_hnr_dmi_cmd;

typedef union{
    _bps_bps_0_clc_hnr_dmi_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_CMD;

typedef struct{
    unsigned  AUTO_LOAD_DONE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hnr_dmi_status;

typedef union{
    _bps_bps_0_clc_hnr_dmi_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_STATUS;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hnr_dmi_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_hnr_dmi_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG;

typedef struct{
    unsigned  BANK_SEL : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hnr_module_lut_bank_cfg;

typedef union{
    _bps_bps_0_clc_hnr_module_lut_bank_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  STRIPE_AUTO_CROP_DIS : 1; /* 1:1 */
    unsigned  UNUSED0 : 6; /* 7:2 */
    unsigned  BLEND_SNR_EN : 1; /* 8:8 */
    unsigned  BLEND_CNR_EN : 1; /* 9:9 */
    unsigned  BLEND_ENABLE : 1; /* 10:10 */
    unsigned  LPF3_EN : 1; /* 11:11 */
    unsigned  FNR_EN : 1; /* 12:12 */
    unsigned  FD_SNR_EN : 1; /* 13:13 */
    unsigned  SNR_EN : 1; /* 14:14 */
    unsigned  CNR_EN : 1; /* 15:15 */
    unsigned  RNR_EN : 1; /* 16:16 */
    unsigned  LNR_EN : 1; /* 17:17 */
    unsigned  UNUSED1 : 14; /* 31:18 */
} _bps_bps_0_clc_hnr_module_cfg;

typedef union{
    _bps_bps_0_clc_hnr_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_MODULE_CFG;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_0 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_1 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_2 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_3 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_0;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_0;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_4 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_5 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_6 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_7 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_1;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_1;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_8 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_9 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_10 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_11 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_2;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_2;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_12 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_13 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_14 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_15 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_3;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_3;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_16 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_17 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_18 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_19 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_4;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_4;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_20 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_21 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_22 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_23 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_5;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_5;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_24 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_25 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_26 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_27 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_6;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_6 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_6;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_28 : 8; /* 7:0 */
    unsigned  FILTERING_NR_GAIN_ARR_29 : 8; /* 15:8 */
    unsigned  FILTERING_NR_GAIN_ARR_30 : 8; /* 23:16 */
    unsigned  FILTERING_NR_GAIN_ARR_31 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_nr_gain_table_7;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_7 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_7;

typedef struct{
    unsigned  FILTERING_NR_GAIN_ARR_32 : 8; /* 7:0 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _bps_bps_0_clc_hnr_nr_gain_table_8;

typedef union{
    _bps_bps_0_clc_hnr_nr_gain_table_8 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_NR_GAIN_TABLE_8;

typedef struct{
    unsigned  CNR_THRD_GAP_V : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  CNR_LOW_THRD_V : 8; /* 11:4 */
    unsigned  CNR_THRD_GAP_U : 3; /* 14:12 */
    unsigned  UNUSED1 : 1; /* 15:15 */
    unsigned  CNR_LOW_THRD_U : 8; /* 23:16 */
    unsigned  UNUSED2 : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_cnr_cfg_0;

typedef union{
    _bps_bps_0_clc_hnr_cnr_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_CFG_0;

typedef struct{
    unsigned  CNR_SCALE : 4; /* 3:0 */
    unsigned  CNR_ADJ_GAIN : 6; /* 9:4 */
    unsigned  UNUSED0 : 22; /* 31:10 */
} _bps_bps_0_clc_hnr_cnr_cfg_1;

typedef union{
    _bps_bps_0_clc_hnr_cnr_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_CFG_1;

typedef struct{
    unsigned  CNR_GAIN_ARR_0 : 6; /* 5:0 */
    unsigned  CNR_GAIN_ARR_1 : 6; /* 11:6 */
    unsigned  CNR_GAIN_ARR_2 : 6; /* 17:12 */
    unsigned  CNR_GAIN_ARR_3 : 6; /* 23:18 */
    unsigned  CNR_GAIN_ARR_4 : 6; /* 29:24 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_cnr_gain_table_0;

typedef union{
    _bps_bps_0_clc_hnr_cnr_gain_table_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_0;

typedef struct{
    unsigned  CNR_GAIN_ARR_5 : 6; /* 5:0 */
    unsigned  CNR_GAIN_ARR_6 : 6; /* 11:6 */
    unsigned  CNR_GAIN_ARR_7 : 6; /* 17:12 */
    unsigned  CNR_GAIN_ARR_8 : 6; /* 23:18 */
    unsigned  CNR_GAIN_ARR_9 : 6; /* 29:24 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_cnr_gain_table_1;

typedef union{
    _bps_bps_0_clc_hnr_cnr_gain_table_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_1;

typedef struct{
    unsigned  CNR_GAIN_ARR_10 : 6; /* 5:0 */
    unsigned  CNR_GAIN_ARR_11 : 6; /* 11:6 */
    unsigned  CNR_GAIN_ARR_12 : 6; /* 17:12 */
    unsigned  CNR_GAIN_ARR_13 : 6; /* 23:18 */
    unsigned  CNR_GAIN_ARR_14 : 6; /* 29:24 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_cnr_gain_table_2;

typedef union{
    _bps_bps_0_clc_hnr_cnr_gain_table_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_2;

typedef struct{
    unsigned  CNR_GAIN_ARR_15 : 6; /* 5:0 */
    unsigned  CNR_GAIN_ARR_16 : 6; /* 11:6 */
    unsigned  CNR_GAIN_ARR_17 : 6; /* 17:12 */
    unsigned  CNR_GAIN_ARR_18 : 6; /* 23:18 */
    unsigned  CNR_GAIN_ARR_19 : 6; /* 29:24 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_cnr_gain_table_3;

typedef union{
    _bps_bps_0_clc_hnr_cnr_gain_table_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_3;

typedef struct{
    unsigned  CNR_GAIN_ARR_20 : 6; /* 5:0 */
    unsigned  CNR_GAIN_ARR_21 : 6; /* 11:6 */
    unsigned  CNR_GAIN_ARR_22 : 6; /* 17:12 */
    unsigned  CNR_GAIN_ARR_23 : 6; /* 23:18 */
    unsigned  CNR_GAIN_ARR_24 : 6; /* 29:24 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_cnr_gain_table_4;

typedef union{
    _bps_bps_0_clc_hnr_cnr_gain_table_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_CNR_GAIN_TABLE_4;

typedef struct{
    unsigned  SNR_SKIN_HUE_MAX : 8; /* 7:0 */
    unsigned  SNR_SKIN_HUE_MIN : 10; /* 17:8 */
    unsigned  UNUSED0 : 2; /* 19:18 */
    unsigned  SNR_SKIN_Y_MIN : 8; /* 27:20 */
    unsigned  SNR_SKIN_SMOOTHING_STR : 2; /* 29:28 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_snr_cfg_0;

typedef union{
    _bps_bps_0_clc_hnr_snr_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_SNR_CFG_0;

typedef struct{
    unsigned  SNR_SKIN_Y_MAX : 8; /* 7:0 */
    unsigned  SNR_QSTEP_SKIN : 8; /* 15:8 */
    unsigned  SNR_QSTEP_NONSKIN : 8; /* 23:16 */
    unsigned  SNR_BOUNDARY_PROBABILITY : 4; /* 27:24 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_snr_cfg_1;

typedef union{
    _bps_bps_0_clc_hnr_snr_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_SNR_CFG_1;

typedef struct{
    unsigned  SNR_SAT_MAX_SLOPE : 8; /* 7:0 */
    unsigned  SNR_SAT_MIN_SLOPE : 8; /* 15:8 */
    unsigned  SNR_SKIN_YMAX_SAT_MAX : 8; /* 23:16 */
    unsigned  SNR_SKIN_YMAX_SAT_MIN : 8; /* 31:24 */
} _bps_bps_0_clc_hnr_snr_cfg_2;

typedef union{
    _bps_bps_0_clc_hnr_snr_cfg_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_SNR_CFG_2;

typedef struct{
    unsigned  FACE_NUM : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_hnr_face_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_CFG;

typedef struct{
    unsigned  FACE_HORIZONTAL_OFFSET : 16; /* 15:0 */
    unsigned  FACE_VERTICAL_OFFSET : 16; /* 31:16 */
} _bps_bps_0_clc_hnr_face_offset_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_offset_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_OFFSET_CFG;

typedef struct{
    unsigned  FACE_CENTER_HORIZONTAL : 16; /* 15:0 */
    unsigned  FACE_CENTER_VERTICAL : 16; /* 31:16 */
} _bps_bps_0_clc_hnr_face_0_center_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_0_center_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_0_CENTER_CFG;

typedef struct{
    unsigned  FACE_CENTER_HORIZONTAL : 16; /* 15:0 */
    unsigned  FACE_CENTER_VERTICAL : 16; /* 31:16 */
} _bps_bps_0_clc_hnr_face_1_center_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_1_center_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_1_CENTER_CFG;

typedef struct{
    unsigned  FACE_CENTER_HORIZONTAL : 16; /* 15:0 */
    unsigned  FACE_CENTER_VERTICAL : 16; /* 31:16 */
} _bps_bps_0_clc_hnr_face_2_center_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_2_center_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_2_CENTER_CFG;

typedef struct{
    unsigned  FACE_CENTER_HORIZONTAL : 16; /* 15:0 */
    unsigned  FACE_CENTER_VERTICAL : 16; /* 31:16 */
} _bps_bps_0_clc_hnr_face_3_center_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_3_center_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_3_CENTER_CFG;

typedef struct{
    unsigned  FACE_CENTER_HORIZONTAL : 16; /* 15:0 */
    unsigned  FACE_CENTER_VERTICAL : 16; /* 31:16 */
} _bps_bps_0_clc_hnr_face_4_center_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_4_center_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_4_CENTER_CFG;

typedef struct{
    unsigned  FACE_RADIUS_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 2; /* 5:4 */
    unsigned  FACE_RADIUS_BOUNDARY : 8; /* 13:6 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  FACE_SLOPE_SHIFT : 3; /* 18:16 */
    unsigned  UNUSED2 : 1; /* 19:19 */
    unsigned  FACE_RADIUS_SLOPE : 8; /* 27:20 */
    unsigned  UNUSED3 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_face_0_radius_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_0_radius_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_0_RADIUS_CFG;

typedef struct{
    unsigned  FACE_RADIUS_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 2; /* 5:4 */
    unsigned  FACE_RADIUS_BOUNDARY : 8; /* 13:6 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  FACE_SLOPE_SHIFT : 3; /* 18:16 */
    unsigned  UNUSED2 : 1; /* 19:19 */
    unsigned  FACE_RADIUS_SLOPE : 8; /* 27:20 */
    unsigned  UNUSED3 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_face_1_radius_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_1_radius_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_1_RADIUS_CFG;

typedef struct{
    unsigned  FACE_RADIUS_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 2; /* 5:4 */
    unsigned  FACE_RADIUS_BOUNDARY : 8; /* 13:6 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  FACE_SLOPE_SHIFT : 3; /* 18:16 */
    unsigned  UNUSED2 : 1; /* 19:19 */
    unsigned  FACE_RADIUS_SLOPE : 8; /* 27:20 */
    unsigned  UNUSED3 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_face_2_radius_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_2_radius_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_2_RADIUS_CFG;

typedef struct{
    unsigned  FACE_RADIUS_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 2; /* 5:4 */
    unsigned  FACE_RADIUS_BOUNDARY : 8; /* 13:6 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  FACE_SLOPE_SHIFT : 3; /* 18:16 */
    unsigned  UNUSED2 : 1; /* 19:19 */
    unsigned  FACE_RADIUS_SLOPE : 8; /* 27:20 */
    unsigned  UNUSED3 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_face_3_radius_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_3_radius_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_3_RADIUS_CFG;

typedef struct{
    unsigned  FACE_RADIUS_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 2; /* 5:4 */
    unsigned  FACE_RADIUS_BOUNDARY : 8; /* 13:6 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  FACE_SLOPE_SHIFT : 3; /* 18:16 */
    unsigned  UNUSED2 : 1; /* 19:19 */
    unsigned  FACE_RADIUS_SLOPE : 8; /* 27:20 */
    unsigned  UNUSED3 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_face_4_radius_cfg;

typedef union{
    _bps_bps_0_clc_hnr_face_4_radius_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_FACE_4_RADIUS_CFG;

typedef struct{
    unsigned  RNR_BASE_0 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_ANCHOR_0 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_hnr_rnr_anchor_base_settings_0;

typedef union{
    _bps_bps_0_clc_hnr_rnr_anchor_base_settings_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_0;

typedef struct{
    unsigned  RNR_BASE_1 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_ANCHOR_1 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_hnr_rnr_anchor_base_settings_1;

typedef union{
    _bps_bps_0_clc_hnr_rnr_anchor_base_settings_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_1;

typedef struct{
    unsigned  RNR_BASE_2 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_ANCHOR_2 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_hnr_rnr_anchor_base_settings_2;

typedef union{
    _bps_bps_0_clc_hnr_rnr_anchor_base_settings_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_2;

typedef struct{
    unsigned  RNR_BASE_3 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_ANCHOR_3 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_hnr_rnr_anchor_base_settings_3;

typedef union{
    _bps_bps_0_clc_hnr_rnr_anchor_base_settings_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_3;

typedef struct{
    unsigned  RNR_BASE_4 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_ANCHOR_4 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_hnr_rnr_anchor_base_settings_4;

typedef union{
    _bps_bps_0_clc_hnr_rnr_anchor_base_settings_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_4;

typedef struct{
    unsigned  RNR_BASE_5 : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  RNR_ANCHOR_5 : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_hnr_rnr_anchor_base_settings_5;

typedef union{
    _bps_bps_0_clc_hnr_rnr_anchor_base_settings_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_ANCHOR_BASE_SETTINGS_5;

typedef struct{
    unsigned  RNR_SHIFT_0 : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  RNR_SLOPE_0 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_hnr_rnr_slope_shift_settings_0;

typedef union{
    _bps_bps_0_clc_hnr_rnr_slope_shift_settings_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_0;

typedef struct{
    unsigned  RNR_SHIFT_1 : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  RNR_SLOPE_1 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_hnr_rnr_slope_shift_settings_1;

typedef union{
    _bps_bps_0_clc_hnr_rnr_slope_shift_settings_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_1;

typedef struct{
    unsigned  RNR_SHIFT_2 : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  RNR_SLOPE_2 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_hnr_rnr_slope_shift_settings_2;

typedef union{
    _bps_bps_0_clc_hnr_rnr_slope_shift_settings_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_2;

typedef struct{
    unsigned  RNR_SHIFT_3 : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  RNR_SLOPE_3 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_hnr_rnr_slope_shift_settings_3;

typedef union{
    _bps_bps_0_clc_hnr_rnr_slope_shift_settings_3 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_3;

typedef struct{
    unsigned  RNR_SHIFT_4 : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  RNR_SLOPE_4 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_hnr_rnr_slope_shift_settings_4;

typedef union{
    _bps_bps_0_clc_hnr_rnr_slope_shift_settings_4 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_4;

typedef struct{
    unsigned  RNR_SHIFT_5 : 4; /* 3:0 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  RNR_SLOPE_5 : 11; /* 26:16 */
    unsigned  UNUSED1 : 5; /* 31:27 */
} _bps_bps_0_clc_hnr_rnr_slope_shift_settings_5;

typedef union{
    _bps_bps_0_clc_hnr_rnr_slope_shift_settings_5 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_SLOPE_SHIFT_SETTINGS_5;

typedef struct{
    unsigned  RNR_BY : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  RNR_BX : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_hnr_rnr_init_hv_offset;

typedef union{
    _bps_bps_0_clc_hnr_rnr_init_hv_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_INIT_HV_OFFSET;

typedef struct{
    unsigned  RNR_R_SQUARE_INIT : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _bps_bps_0_clc_hnr_rnr_r_square_init;

typedef union{
    _bps_bps_0_clc_hnr_rnr_r_square_init bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_R_SQUARE_INIT;

typedef struct{
    unsigned  RNR_R_SQUARE_SHIFT : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  RNR_R_SQUARE_SCALE : 7; /* 14:8 */
    unsigned  UNUSED1 : 17; /* 31:15 */
} _bps_bps_0_clc_hnr_rnr_r_scale_shift;

typedef union{
    _bps_bps_0_clc_hnr_rnr_r_scale_shift bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_RNR_R_SCALE_SHIFT;

typedef struct{
    unsigned  LPF3_OFFSET : 8; /* 7:0 */
    unsigned  LPF3_PERCENT : 8; /* 15:8 */
    unsigned  LPF3_STRENGTH : 3; /* 18:16 */
    unsigned  UNUSED0 : 13; /* 31:19 */
} _bps_bps_0_clc_hnr_lpf3_cfg;

typedef union{
    _bps_bps_0_clc_hnr_lpf3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_LPF3_CFG;

typedef struct{
    unsigned  BLEND_CNR_ADJ_GAIN : 6; /* 5:0 */
    unsigned  UNUSED0 : 2; /* 7:6 */
    unsigned  ABS_AMP_SHIFT : 2; /* 9:8 */
    unsigned  UNUSED1 : 2; /* 11:10 */
    unsigned  FNR_AC_SHIFT : 2; /* 13:12 */
    unsigned  UNUSED2 : 2; /* 15:14 */
    unsigned  LNR_SHIFT : 2; /* 17:16 */
    unsigned  UNUSED3 : 14; /* 31:18 */
} _bps_bps_0_clc_hnr_misc_cfg;

typedef union{
    _bps_bps_0_clc_hnr_misc_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_MISC_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_hnr_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_hnr_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_hnr_spare;

typedef union{
    _bps_bps_0_clc_hnr_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_HNR_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  FLUSH_PACE_CNT : 5; /* 12:8 */
    unsigned  UNUSED1 : 3; /* 15:13 */
    unsigned  HEIGHT : 15; /* 30:16 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  COEFF_07 : 9; /* 8:0 */
    unsigned  UNUSED0 : 1; /* 9:9 */
    unsigned  COEFF_16 : 9; /* 18:10 */
    unsigned  UNUSED1 : 1; /* 19:19 */
    unsigned  COEFF_25 : 9; /* 28:20 */
    unsigned  UNUSED2 : 3; /* 31:29 */
} _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_ds_coeff;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_ds_coeff bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_DS_COEFF;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  FLUSH_PACE_CNT : 5; /* 12:8 */
    unsigned  UNUSED1 : 3; /* 15:13 */
    unsigned  HEIGHT : 14; /* 29:16 */
    unsigned  UNUSED2 : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_r2pd_full_ds4_out_hw_version;

typedef union{
    _bps_bps_0_clc_r2pd_full_ds4_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_r2pd_full_ds4_out_hw_status;

typedef union{
    _bps_bps_0_clc_r2pd_full_ds4_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  PACK_MODE : 1; /* 8:8 */
    unsigned  UNUSED1 : 3; /* 11:9 */
    unsigned  FLUSH_PACE_CNT : 5; /* 16:12 */
    unsigned  UNUSED2 : 15; /* 31:17 */
} _bps_bps_0_clc_r2pd_full_ds4_out_module_cfg;

typedef union{
    _bps_bps_0_clc_r2pd_full_ds4_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_MODULE_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_r2pd_full_ds4_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_r2pd_full_ds4_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_r2pd_full_ds4_out_spare;

typedef union{
    _bps_bps_0_clc_r2pd_full_ds4_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_FULL_DS4_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_downscale_4to1_y_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_y_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  FLUSH_PACE_CNT : 5; /* 12:8 */
    unsigned  UNUSED1 : 3; /* 15:13 */
    unsigned  HEIGHT : 15; /* 30:16 */
    unsigned  UNUSED2 : 1; /* 31:31 */
} _bps_bps_0_clc_downscale_4to1_y_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  COEFF_07 : 9; /* 8:0 */
    unsigned  UNUSED0 : 1; /* 9:9 */
    unsigned  COEFF_16 : 9; /* 18:10 */
    unsigned  UNUSED1 : 1; /* 19:19 */
    unsigned  COEFF_25 : 9; /* 28:20 */
    unsigned  UNUSED2 : 3; /* 31:29 */
} _bps_bps_0_clc_downscale_4to1_y_ds16_out_ds_coeff;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_ds16_out_ds_coeff bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_DS_COEFF;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_downscale_4to1_y_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_y_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_downscale_4to1_y_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_Y_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_downscale_4to1_c_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_c_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  FLUSH_PACE_CNT : 5; /* 12:8 */
    unsigned  UNUSED1 : 3; /* 15:13 */
    unsigned  HEIGHT : 14; /* 29:16 */
    unsigned  UNUSED2 : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_4to1_c_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_downscale_4to1_c_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_4to1_c_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_downscale_4to1_c_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_4TO1_C_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_r2pd_ds16_out_hw_version;

typedef union{
    _bps_bps_0_clc_r2pd_ds16_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_r2pd_ds16_out_hw_status;

typedef union{
    _bps_bps_0_clc_r2pd_ds16_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_DS16_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  PACK_MODE : 1; /* 8:8 */
    unsigned  UNUSED1 : 3; /* 11:9 */
    unsigned  FLUSH_PACE_CNT : 5; /* 16:12 */
    unsigned  UNUSED2 : 15; /* 31:17 */
} _bps_bps_0_clc_r2pd_ds16_out_module_cfg;

typedef union{
    _bps_bps_0_clc_r2pd_ds16_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_DS16_OUT_MODULE_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 4; /* 7:4 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _bps_bps_0_clc_r2pd_ds16_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_r2pd_ds16_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_DS16_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_r2pd_ds16_out_spare;

typedef union{
    _bps_bps_0_clc_r2pd_ds16_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_R2PD_DS16_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_y_reg_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_Y_REG_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_pre_downscale_c_reg_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_PRE_DOWNSCALE_C_REG_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_hw_version;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  OVERFLOW_ERROR : 1; /* 1:1 */
    unsigned  OVERWRITE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_hw_status;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_module_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_MODULE_CFG;

typedef struct{
    unsigned  UNUSED0 : 9; /* 8:0 */
    unsigned  HORIZONTAL_SCALE_EN : 1; /* 9:9 */
    unsigned  VERTICAL_SCALE_EN : 1; /* 10:10 */
    unsigned  UNUSED1 : 1; /* 11:11 */
    unsigned  HORIZONTAL_ROUNDING : 2; /* 13:12 */
    unsigned  UNUSED2 : 1; /* 14:14 */
    unsigned  VERTICAL_ROUNDING : 2; /* 16:15 */
    unsigned  UNUSED3 : 1; /* 17:17 */
    unsigned  HORIZONTAL_TERMINATION_EN : 1; /* 18:18 */
    unsigned  VERTICAL_TERMINATION_EN : 1; /* 19:19 */
    unsigned  UNUSED4 : 12; /* 31:20 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_CFG;

typedef struct{
    unsigned  INPUT_HEIGHT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  INPUT_WIDTH : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_image_size_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_image_size_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_IMAGE_SIZE_CFG;

typedef struct{
    unsigned  PHASE_STEP_H : 29; /* 28:0 */
    unsigned  UNUSED0 : 1; /* 29:29 */
    unsigned  H_INTERP_RESO : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_h_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_h_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_CFG;

typedef struct{
    unsigned  PHASE_INIT_H : 29; /* 28:0 */
    unsigned  UNUSED0 : 3; /* 31:29 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_h_phase_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_h_phase_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_H_PHASE_CFG;

typedef struct{
    unsigned  PHASE_STEP_V : 29; /* 28:0 */
    unsigned  UNUSED0 : 1; /* 29:29 */
    unsigned  V_INTERP_RESO : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_v_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_v_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_CFG;

typedef struct{
    unsigned  PHASE_INIT_V : 29; /* 28:0 */
    unsigned  UNUSED0 : 3; /* 31:29 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_v_phase_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_downscale_mn_y_v_phase_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_DOWNSCALE_MN_Y_V_PHASE_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_mn_y_reg_out_spare;

typedef union{
    _bps_bps_0_clc_downscale_mn_y_reg_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_Y_REG_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_hw_version;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  OVERFLOW_ERROR : 1; /* 1:1 */
    unsigned  OVERWRITE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_hw_status;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_module_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_MODULE_CFG;

typedef struct{
    unsigned  UNUSED0 : 9; /* 8:0 */
    unsigned  HORIZONTAL_SCALE_EN : 1; /* 9:9 */
    unsigned  VERTICAL_SCALE_EN : 1; /* 10:10 */
    unsigned  UNUSED1 : 1; /* 11:11 */
    unsigned  HORIZONTAL_ROUNDING : 2; /* 13:12 */
    unsigned  UNUSED2 : 1; /* 14:14 */
    unsigned  VERTICAL_ROUNDING : 2; /* 16:15 */
    unsigned  UNUSED3 : 1; /* 17:17 */
    unsigned  HORIZONTAL_TERMINATION_EN : 1; /* 18:18 */
    unsigned  VERTICAL_TERMINATION_EN : 1; /* 19:19 */
    unsigned  UNUSED4 : 12; /* 31:20 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_CFG;

typedef struct{
    unsigned  INPUT_HEIGHT : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  INPUT_WIDTH : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_image_size_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_image_size_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_IMAGE_SIZE_CFG;

typedef struct{
    unsigned  PHASE_STEP_H : 29; /* 28:0 */
    unsigned  UNUSED0 : 1; /* 29:29 */
    unsigned  H_INTERP_RESO : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_h_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_h_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_CFG;

typedef struct{
    unsigned  PHASE_INIT_H : 29; /* 28:0 */
    unsigned  UNUSED0 : 3; /* 31:29 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_h_phase_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_h_phase_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_H_PHASE_CFG;

typedef struct{
    unsigned  PHASE_STEP_V : 29; /* 28:0 */
    unsigned  UNUSED0 : 1; /* 29:29 */
    unsigned  V_INTERP_RESO : 2; /* 31:30 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_v_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_v_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_CFG;

typedef struct{
    unsigned  PHASE_INIT_V : 29; /* 28:0 */
    unsigned  UNUSED0 : 3; /* 31:29 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_v_phase_cfg;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_downscale_mn_c_v_phase_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_DOWNSCALE_MN_C_V_PHASE_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_downscale_mn_c_reg_out_spare;

typedef union{
    _bps_bps_0_clc_downscale_mn_c_reg_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_DOWNSCALE_MN_C_REG_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_y_reg_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_Y_REG_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_hw_version;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_hw_status;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_HW_STATUS;

typedef struct{
    unsigned  CROP_RND_CLAMP_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 8; /* 8:1 */
    unsigned  CROP_EN : 1; /* 9:9 */
    unsigned  CH0_ROUND_EN : 1; /* 10:10 */
    unsigned  CH0_CLAMP_EN : 1; /* 11:11 */
    unsigned  CH1_ROUND_EN : 1; /* 12:12 */
    unsigned  CH1_CLAMP_EN : 1; /* 13:13 */
    unsigned  CH2_ROUND_EN : 1; /* 14:14 */
    unsigned  CH2_CLAMP_EN : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_module_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_MODULE_CFG;

typedef struct{
    unsigned  LAST_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_crop_line_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_crop_line_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_LINE_CFG;

typedef struct{
    unsigned  LAST_PIXEL : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  FIRST_PIXEL : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_crop_pixel_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_crop_pixel_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CROP_PIXEL_CFG;

typedef struct{
    unsigned  CH0_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH0_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch0_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch0_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_CLAMP_CFG;

typedef struct{
    unsigned  CH0_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH0_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH0_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch0_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch0_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH0_ROUNDING_CFG;

typedef struct{
    unsigned  CH1_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH1_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch1_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch1_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_CLAMP_CFG;

typedef struct{
    unsigned  CH1_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH1_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH1_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch1_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch1_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH1_ROUNDING_CFG;

typedef struct{
    unsigned  CH2_CLAMP_MIN : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  CH2_CLAMP_MAX : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch2_clamp_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch2_clamp_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_CLAMP_CFG;

typedef struct{
    unsigned  CH2_INTERLEAVED : 1; /* 0:0 */
    unsigned  CH2_ROUNDING_PATTERN : 2; /* 2:1 */
    unsigned  CH2_ROUND_OFF_BITS : 3; /* 5:3 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch2_rounding_cfg;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_ch2_rounding_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_CH2_ROUNDING_CFG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_test_bus_ctrl;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_spare;

typedef union{
    _bps_bps_0_clc_crop_rnd_clamp_post_downscale_c_reg_out_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_C_REG_OUT_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_bus_rd_hw_version;

typedef union{
    _bps_bps_0_bus_rd_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_HW_VERSION;

typedef struct{
    unsigned  REG : 8; /* 7:0 */
    unsigned  UBWC : 8; /* 15:8 */
    unsigned  LITE : 8; /* 23:16 */
    unsigned  FEATURE : 8; /* 31:24 */
} _bps_bps_0_bus_rd_hw_capability;

typedef union{
    _bps_bps_0_bus_rd_hw_capability bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_HW_CAPABILITY;

typedef struct{
    unsigned  RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_rd_input_if_sw_reset;

typedef union{
    _bps_bps_0_bus_rd_input_if_sw_reset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_SW_RESET;

typedef struct{
    unsigned  CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_rd_input_if_cgc_override;

typedef union{
    _bps_bps_0_bus_rd_input_if_cgc_override bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_CGC_OVERRIDE;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  INFO_CCIF_VIOLATION : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _bps_bps_0_bus_rd_input_if_irq_mask;

typedef union{
    _bps_bps_0_bus_rd_input_if_irq_mask bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_MASK;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  INFO_CCIF_VIOLATION : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _bps_bps_0_bus_rd_input_if_irq_clear;

typedef union{
    _bps_bps_0_bus_rd_input_if_irq_clear bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CLEAR;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _bps_bps_0_bus_rd_input_if_irq_cmd;

typedef union{
    _bps_bps_0_bus_rd_input_if_irq_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_CMD;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  INFO_CCIF_VIOLATION : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _bps_bps_0_bus_rd_input_if_irq_status;

typedef union{
    _bps_bps_0_bus_rd_input_if_irq_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_STATUS;

typedef struct{
    unsigned  GO_CMD : 1; /* 0:0 */
    unsigned  ICA_EN : 1; /* 1:1 */
    unsigned  UNUSED0 : 1; /* 2:2 */
    unsigned  STATIC_PRG : 1; /* 3:3 */
    unsigned  UNUSED1 : 28; /* 31:4 */
} _bps_bps_0_bus_rd_input_if_cmd;

typedef union{
    _bps_bps_0_bus_rd_input_if_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_CMD;

typedef struct{
    unsigned  INFO_RST_DONE : 1; /* 0:0 */
    unsigned  INFO_REG_UPDATE_DONE : 1; /* 1:1 */
    unsigned  INFO_RD_CLIENT_BUF_DONE : 1; /* 2:2 */
    unsigned  UNUSED0 : 13; /* 15:3 */
    unsigned  INFO_CCIF_VIOLATION : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _bps_bps_0_bus_rd_input_if_irq_set;

typedef union{
    _bps_bps_0_bus_rd_input_if_irq_set bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_IRQ_SET;

typedef struct{
    unsigned  RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_rd_input_if_misr_reset;

typedef union{
    _bps_bps_0_bus_rd_input_if_misr_reset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_MISR_RESET;

typedef struct{
    unsigned  ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_rd_input_if_security_cfg;

typedef union{
    _bps_bps_0_bus_rd_input_if_security_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_INPUT_IF_SECURITY_CFG;

typedef struct{
    unsigned  PWR_ISO_ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 1; /* 1:1 */
    unsigned  PWR_ISO_PATGEN_SELECT : 2; /* 3:2 */
    unsigned  UNUSED1 : 1; /* 4:4 */
    unsigned  PWR_ISO_BPP_SELECT : 2; /* 6:5 */
    unsigned  UNUSED2 : 25; /* 31:7 */
} _bps_bps_0_bus_rd_pwr_iso_cfg;

typedef union{
    _bps_bps_0_bus_rd_pwr_iso_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_PWR_ISO_CFG;

typedef struct{
    unsigned  PWR_ISO_PATGEN_SEED : 32; /* 31:0 */
} _bps_bps_0_bus_rd_pwr_iso_seed;

typedef union{
    _bps_bps_0_bus_rd_pwr_iso_seed bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_PWR_ISO_SEED;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_CLIENT_SEL : 5; /* 8:4 */
    unsigned  TEST_BUS_INTERNAL_SEL : 7; /* 15:9 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_bus_rd_test_bus_ctrl;

typedef union{
    _bps_bps_0_bus_rd_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_rd_spare;

typedef union{
    _bps_bps_0_bus_rd_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_SPARE;

typedef struct{
    unsigned  CLIENT_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_rd_client_0_core_cfg;

typedef union{
    _bps_bps_0_bus_rd_client_0_core_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_CORE_CFG;

typedef struct{
    unsigned  STRIPE_LOCATION : 2; /* 1:0 */
    unsigned  PIXEL_PATTERN : 6; /* 7:2 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _bps_bps_0_bus_rd_client_0_ccif_meta_data;

typedef union{
    _bps_bps_0_bus_rd_client_0_ccif_meta_data bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_rd_client_0_addr_image;

typedef union{
    _bps_bps_0_bus_rd_client_0_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_ADDR_IMAGE;

typedef struct{
    unsigned  WIDTH : 16; /* 15:0 */
    unsigned  HEIGHT : 16; /* 31:16 */
} _bps_bps_0_bus_rd_client_0_rd_buffer_size;

typedef union{
    _bps_bps_0_bus_rd_client_0_rd_buffer_size bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_RD_BUFFER_SIZE;

typedef struct{
    unsigned  STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_rd_client_0_rd_stride;

typedef union{
    _bps_bps_0_bus_rd_client_0_rd_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_RD_STRIDE;

typedef struct{
    unsigned  MODE : 5; /* 4:0 */
    unsigned  ALIGNMENT : 1; /* 5:5 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_bus_rd_client_0_unpack_cfg_0;

typedef union{
    _bps_bps_0_bus_rd_client_0_unpack_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0;

typedef struct{
    unsigned  BUFF_SIZE : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_rd_client_0_latency_buff_allocation;

typedef union{
    _bps_bps_0_bus_rd_client_0_latency_buff_allocation bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_LATENCY_BUFF_ALLOCATION;

typedef struct{
    unsigned  BURST_LENGTH_MAX : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_rd_client_0_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_rd_client_0_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_BURST_LIMIT_CFG;

typedef struct{
    unsigned  SAMP_MODE : 2; /* 1:0 */
    unsigned  ENABLE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_rd_client_0_misr_cfg_0;

typedef union{
    _bps_bps_0_bus_rd_client_0_misr_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_0;

typedef struct{
    unsigned  RD_WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_rd_client_0_misr_cfg_1;

typedef union{
    _bps_bps_0_bus_rd_client_0_misr_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1;

typedef struct{
    unsigned  MISR_VAL : 32; /* 31:0 */
} _bps_bps_0_bus_rd_client_0_misr_rd_val;

typedef union{
    _bps_bps_0_bus_rd_client_0_misr_rd_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_MISR_RD_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_rd_client_0_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_rd_client_0_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_rd_client_0_debug_status_0;

typedef union{
    _bps_bps_0_bus_rd_client_0_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_rd_client_0_debug_status_1;

typedef union{
    _bps_bps_0_bus_rd_client_0_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_RD_CLIENT_0_DEBUG_STATUS_1;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_bus_wr_hw_version;

typedef union{
    _bps_bps_0_bus_wr_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_HW_VERSION;

typedef struct{
    unsigned  FEATURE : 8; /* 7:0 */
    unsigned  LITE : 8; /* 15:8 */
    unsigned  UBWC : 8; /* 23:16 */
    unsigned  REG : 8; /* 31:24 */
} _bps_bps_0_bus_wr_hw_capability;

typedef union{
    _bps_bps_0_bus_wr_hw_capability bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_HW_CAPABILITY;

typedef struct{
    unsigned  SW_RESET : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _bps_bps_0_bus_wr_input_if_sw_reset;

typedef union{
    _bps_bps_0_bus_wr_input_if_sw_reset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_SW_RESET;

typedef struct{
    unsigned  CGC_OVERRIGE : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _bps_bps_0_bus_wr_input_if_cgc_override;

typedef union{
    _bps_bps_0_bus_wr_input_if_cgc_override bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_CGC_OVERRIDE;

typedef struct{
    unsigned  MASK_VEC : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _bps_bps_0_bus_wr_input_if_composite_mask_0;

typedef union{
    _bps_bps_0_bus_wr_input_if_composite_mask_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_COMPOSITE_MASK_0;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _bps_bps_0_bus_wr_input_if_irq_mask_0;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_mask_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 7; /* 6:0 */
    unsigned  UNUSED0 : 17; /* 23:7 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_bus_wr_input_if_irq_mask_1;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_mask_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_MASK_1;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _bps_bps_0_bus_wr_input_if_irq_clear_0;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_clear_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 7; /* 6:0 */
    unsigned  UNUSED0 : 17; /* 23:7 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_bus_wr_input_if_irq_clear_1;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_clear_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CLEAR_1;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _bps_bps_0_bus_wr_input_if_irq_status_0;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 7; /* 6:0 */
    unsigned  UNUSED0 : 17; /* 23:7 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_bus_wr_input_if_irq_status_1;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_STATUS_1;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_input_if_irq_cmd;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_cmd bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_CMD;

typedef struct{
    unsigned  FIFO_STATUS : 7; /* 6:0 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _bps_bps_0_bus_wr_input_if_addr_fifo_status;

typedef union{
    _bps_bps_0_bus_wr_input_if_addr_fifo_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS;

typedef struct{
    unsigned  CFG0 : 32; /* 31:0 */
} _bps_bps_0_bus_wr_input_if_frame_header_cfg0;

typedef union{
    _bps_bps_0_bus_wr_input_if_frame_header_cfg0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0;

typedef struct{
    unsigned  CFG1 : 32; /* 31:0 */
} _bps_bps_0_bus_wr_input_if_frame_header_cfg1;

typedef union{
    _bps_bps_0_bus_wr_input_if_frame_header_cfg1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _bps_bps_0_bus_wr_input_if_irq_set_0;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_set_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 7; /* 6:0 */
    unsigned  UNUSED0 : 17; /* 23:7 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_bus_wr_input_if_irq_set_1;

typedef union{
    _bps_bps_0_bus_wr_input_if_irq_set_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_IRQ_SET_1;

typedef struct{
    unsigned  RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_wr_input_if_misr_reset;

typedef union{
    _bps_bps_0_bus_wr_input_if_misr_reset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_INPUT_IF_MISR_RESET;

typedef struct{
    unsigned  PWR_ISO_ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_wr_pwr_iso_cfg;

typedef union{
    _bps_bps_0_bus_wr_pwr_iso_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_PWR_ISO_CFG;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_CLIENT_SEL : 5; /* 8:4 */
    unsigned  TEST_BUS_INTERNAL_SEL : 7; /* 15:9 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_test_bus_ctrl;

typedef union{
    _bps_bps_0_bus_wr_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_wr_spare;

typedef union{
    _bps_bps_0_bus_wr_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_SPARE;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_0_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_0_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_0_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_0_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_0_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_0_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_0_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_0_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_0_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_0_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_WR_STRIDE;

typedef struct{
    unsigned  TILE_PER_BLK_ROW : 8; /* 7:0 */
    unsigned  TILE_PER_BLK_COL : 8; /* 15:8 */
    unsigned  PARTIAL_TILE_LEFT : 7; /* 22:16 */
    unsigned  PARTIAL_TILE_RIGHT : 7; /* 29:23 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_bus_wr_client_0_tile_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_tile_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_TILE_CFG;

typedef struct{
    unsigned  H_INIT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_0_h_init;

typedef union{
    _bps_bps_0_bus_wr_client_0_h_init bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_H_INIT;

typedef struct{
    unsigned  V_INIT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_0_v_init;

typedef union{
    _bps_bps_0_bus_wr_client_0_v_init bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_V_INIT;

typedef struct{
    unsigned  ADDR_META : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_addr_ubwc_meta;

typedef union{
    _bps_bps_0_bus_wr_client_0_addr_ubwc_meta bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META;

typedef struct{
    unsigned  META_OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_addr_ubwc_meta_offset;

typedef union{
    _bps_bps_0_bus_wr_client_0_addr_ubwc_meta_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_ADDR_UBWC_META_OFFSET;

typedef struct{
    unsigned  UBWC_META_STRIDE : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_0_ubwc_meta_stride;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_meta_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_META_STRIDE;

typedef struct{
    unsigned  UBWC_EN : 1; /* 0:0 */
    unsigned  COMPRESS_EN : 1; /* 1:1 */
    unsigned  UBWC_BANKSPREAD_EN : 1; /* 2:2 */
    unsigned  UBWC_HIGHESTBANKBIT_EN : 1; /* 3:3 */
    unsigned  UBWC_HIGHESTBANK_LV1_EN : 1; /* 4:4 */
    unsigned  UBWC_HIGHESTBANKBIT_VAL : 5; /* 9:5 */
    unsigned  UBWC_MODE_SEL : 3; /* 12:10 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  UBWC_8CHANNEL_EN : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _bps_bps_0_bus_wr_client_0_ubwc_mode_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_mode_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_0_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_0_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_0_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_0_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_0_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_0_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_0_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_0_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_0_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_0_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_0_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_0_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_DEBUG_STATUS_1;

typedef struct{
    unsigned  GEN_STATS : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_wr_client_0_ubwc_stats_ctrl;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_stats_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_STATS_CTRL;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_32b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_32b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_32B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_64b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_64b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_64B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_96b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_96b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_96B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_128b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_128b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_128B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_160b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_160b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_160B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_192b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_192b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_192B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_0_ubwc_compressed_256b;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_compressed_256b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_COMPRESSED_256B;

typedef struct{
    unsigned  ENABLE : 1; /* 0:0 */
    unsigned  COUNTER_LIMIT : 8; /* 8:1 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _bps_bps_0_bus_wr_client_0_ubwc_bw_limit;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_bw_limit bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_BW_LIMIT;

typedef struct{
    unsigned  UBWC_VER : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  LOSSY_MODE : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_0_ubwc_mode_cfg_1;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_mode_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_MODE_CFG_1;

typedef struct{
    unsigned  MIN_DELTA_DARK_0 : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  MIN_DELTA_DARK_1 : 2; /* 5:4 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  MIN_DELTA_DARK_2 : 2; /* 9:8 */
    unsigned  UNUSED2 : 6; /* 15:10 */
    unsigned  COUNT_THRESH_MIN : 3; /* 18:16 */
    unsigned  UNUSED3 : 1; /* 19:19 */
    unsigned  LOSSY_INIT_VAL : 3; /* 22:20 */
    unsigned  UNUSED4 : 1; /* 23:23 */
    unsigned  THRESH_PIX_SUM_DEPTH : 4; /* 27:24 */
    unsigned  UNUSED5 : 4; /* 31:28 */
} _bps_bps_0_bus_wr_client_0_ubwc_threshold_lossy_0;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_threshold_lossy_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_0;

typedef struct{
    unsigned  MIN_DELTA_BRIGHT_0 : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  MIN_DELTA_BRIGHT_1 : 4; /* 11:8 */
    unsigned  UNUSED1 : 4; /* 15:12 */
    unsigned  MIN_DELTA_BRIGHT_2 : 4; /* 19:16 */
    unsigned  UNUSED2 : 12; /* 31:20 */
} _bps_bps_0_bus_wr_client_0_ubwc_threshold_lossy_1;

typedef union{
    _bps_bps_0_bus_wr_client_0_ubwc_threshold_lossy_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_0_UBWC_THRESHOLD_LOSSY_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_1_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_1_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_1_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_1_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_1_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_1_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_1_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_1_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_1_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_1_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_WR_STRIDE;

typedef struct{
    unsigned  TILE_PER_BLK_ROW : 8; /* 7:0 */
    unsigned  TILE_PER_BLK_COL : 8; /* 15:8 */
    unsigned  PARTIAL_TILE_LEFT : 7; /* 22:16 */
    unsigned  PARTIAL_TILE_RIGHT : 7; /* 29:23 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _bps_bps_0_bus_wr_client_1_tile_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_tile_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_TILE_CFG;

typedef struct{
    unsigned  H_INIT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_1_h_init;

typedef union{
    _bps_bps_0_bus_wr_client_1_h_init bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_H_INIT;

typedef struct{
    unsigned  V_INIT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_1_v_init;

typedef union{
    _bps_bps_0_bus_wr_client_1_v_init bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_V_INIT;

typedef struct{
    unsigned  ADDR_META : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_addr_ubwc_meta;

typedef union{
    _bps_bps_0_bus_wr_client_1_addr_ubwc_meta bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META;

typedef struct{
    unsigned  META_OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_addr_ubwc_meta_offset;

typedef union{
    _bps_bps_0_bus_wr_client_1_addr_ubwc_meta_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_ADDR_UBWC_META_OFFSET;

typedef struct{
    unsigned  UBWC_META_STRIDE : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_1_ubwc_meta_stride;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_meta_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_META_STRIDE;

typedef struct{
    unsigned  UBWC_EN : 1; /* 0:0 */
    unsigned  COMPRESS_EN : 1; /* 1:1 */
    unsigned  UBWC_BANKSPREAD_EN : 1; /* 2:2 */
    unsigned  UBWC_HIGHESTBANKBIT_EN : 1; /* 3:3 */
    unsigned  UBWC_HIGHESTBANK_LV1_EN : 1; /* 4:4 */
    unsigned  UBWC_HIGHESTBANKBIT_VAL : 5; /* 9:5 */
    unsigned  UBWC_MODE_SEL : 3; /* 12:10 */
    unsigned  UNUSED0 : 3; /* 15:13 */
    unsigned  UBWC_8CHANNEL_EN : 1; /* 16:16 */
    unsigned  UNUSED1 : 15; /* 31:17 */
} _bps_bps_0_bus_wr_client_1_ubwc_mode_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_mode_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_1_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_1_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_1_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_1_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_1_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_1_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_1_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_1_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_1_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_1_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_1_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_1_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_DEBUG_STATUS_1;

typedef struct{
    unsigned  GEN_STATS : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_bus_wr_client_1_ubwc_stats_ctrl;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_stats_ctrl bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_STATS_CTRL;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_32b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_32b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_32B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_64b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_64b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_64B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_96b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_96b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_96B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_128b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_128b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_128B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_160b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_160b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_160B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_192b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_192b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_192B;

typedef struct{
    unsigned  NUM_UNITS : 18; /* 17:0 */
    unsigned  UNUSED0 : 14; /* 31:18 */
} _bps_bps_0_bus_wr_client_1_ubwc_compressed_256b;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_compressed_256b bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_COMPRESSED_256B;

typedef struct{
    unsigned  ENABLE : 1; /* 0:0 */
    unsigned  COUNTER_LIMIT : 8; /* 8:1 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _bps_bps_0_bus_wr_client_1_ubwc_bw_limit;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_bw_limit bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_BW_LIMIT;

typedef struct{
    unsigned  UBWC_VER : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  LOSSY_MODE : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_1_ubwc_mode_cfg_1;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_mode_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_MODE_CFG_1;

typedef struct{
    unsigned  MIN_DELTA_DARK_0 : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  MIN_DELTA_DARK_1 : 2; /* 5:4 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  MIN_DELTA_DARK_2 : 2; /* 9:8 */
    unsigned  UNUSED2 : 6; /* 15:10 */
    unsigned  COUNT_THRESH_MIN : 3; /* 18:16 */
    unsigned  UNUSED3 : 1; /* 19:19 */
    unsigned  LOSSY_INIT_VAL : 3; /* 22:20 */
    unsigned  UNUSED4 : 1; /* 23:23 */
    unsigned  THRESH_PIX_SUM_DEPTH : 4; /* 27:24 */
    unsigned  UNUSED5 : 4; /* 31:28 */
} _bps_bps_0_bus_wr_client_1_ubwc_threshold_lossy_0;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_threshold_lossy_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_0;

typedef struct{
    unsigned  MIN_DELTA_BRIGHT_0 : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  MIN_DELTA_BRIGHT_1 : 4; /* 11:8 */
    unsigned  UNUSED1 : 4; /* 15:12 */
    unsigned  MIN_DELTA_BRIGHT_2 : 4; /* 19:16 */
    unsigned  UNUSED2 : 12; /* 31:20 */
} _bps_bps_0_bus_wr_client_1_ubwc_threshold_lossy_1;

typedef union{
    _bps_bps_0_bus_wr_client_1_ubwc_threshold_lossy_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_1_UBWC_THRESHOLD_LOSSY_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_2_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_2_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_2_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_2_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_2_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_2_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_2_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_2_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_2_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_2_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_2_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_2_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_2_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_2_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_2_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_2_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_2_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_2_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_2_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_2_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_2_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_2_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_2_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_3_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_3_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_3_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_3_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_3_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_3_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_3_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_3_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_3_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_3_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_3_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_3_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_3_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_3_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_3_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_3_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_3_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_3_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_3_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_3_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_3_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_3_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_3_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_4_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_4_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_4_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_4_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_4_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_4_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_4_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_4_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_4_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_4_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_4_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_4_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_4_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_4_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_4_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_4_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_4_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_4_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_4_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_4_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_4_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_4_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_4_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_5_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_5_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_5_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_5_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_5_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_5_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_5_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_5_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_5_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_5_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_5_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_5_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_5_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_5_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_5_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_5_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_5_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_5_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_5_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_5_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_5_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_5_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_5_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_6_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_6_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_6_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_addr_frame_header;

typedef union{
    _bps_bps_0_bus_wr_client_6_addr_frame_header bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_frame_header_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_addr_image;

typedef union{
    _bps_bps_0_bus_wr_client_6_addr_image bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_addr_image_offset;

typedef union{
    _bps_bps_0_bus_wr_client_6_addr_image_offset bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_buffer_width_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_6_buffer_height_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _bps_bps_0_bus_wr_client_6_packer_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_packer_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _bps_bps_0_bus_wr_client_6_wr_stride;

typedef union{
    _bps_bps_0_bus_wr_client_6_wr_stride bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_irq_subsample_cfg_period;

typedef union{
    _bps_bps_0_bus_wr_client_6_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_irq_subsample_cfg_pattern;

typedef union{
    _bps_bps_0_bus_wr_client_6_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _bps_bps_0_bus_wr_client_6_burst_limit_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _bps_bps_0_bus_wr_client_6_misr_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_misr_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _bps_bps_0_bus_wr_client_6_misr_rd_word_sel;

typedef union{
    _bps_bps_0_bus_wr_client_6_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_misr_val;

typedef union{
    _bps_bps_0_bus_wr_client_6_misr_val bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _bps_bps_0_bus_wr_client_6_debug_status_cfg;

typedef union{
    _bps_bps_0_bus_wr_client_6_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_debug_status_0;

typedef union{
    _bps_bps_0_bus_wr_client_6_debug_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _bps_bps_0_bus_wr_client_6_debug_status_1;

typedef union{
    _bps_bps_0_bus_wr_client_6_debug_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_BUS_WR_CLIENT_6_DEBUG_STATUS_1;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _bps_bps_0_qos_hw_version;

typedef union{
    _bps_bps_0_qos_hw_version bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_HW_VERSION;

typedef struct{
    unsigned  VIOLATION : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_qos_hw_status;

typedef union{
    _bps_bps_0_qos_hw_status bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_HW_STATUS;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 7; /* 7:1 */
    unsigned  STATIC_HEALTH : 4; /* 11:8 */
    unsigned  UNUSED1 : 4; /* 15:12 */
    unsigned  PROC_INTERVAL : 10; /* 25:16 */
    unsigned  UNUSED2 : 6; /* 31:26 */
} _bps_bps_0_qos_module_cfg;

typedef union{
    _bps_bps_0_qos_module_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_MODULE_CFG;

typedef struct{
    unsigned  YMIN_INC : 10; /* 9:0 */
    unsigned  UNUSED0 : 6; /* 15:10 */
    unsigned  YEXP_YMIN_DEC : 10; /* 25:16 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _bps_bps_0_qos_curve_cfg_0;

typedef union{
    _bps_bps_0_qos_curve_cfg_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_CURVE_CFG_0;

typedef struct{
    unsigned  INITIAL_DELTA : 26; /* 25:0 */
    unsigned  UNUSED0 : 6; /* 31:26 */
} _bps_bps_0_qos_curve_cfg_1;

typedef union{
    _bps_bps_0_qos_curve_cfg_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_CURVE_CFG_1;

typedef struct{
    unsigned  SESSION_CNT : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _bps_bps_0_qos_window_cfg;

typedef union{
    _bps_bps_0_qos_window_cfg bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_WINDOW_CFG;

typedef struct{
    unsigned  EOS_ID : 1; /* 0:0 */
    unsigned  EOS_YEXP_YMIN : 27; /* 27:1 */
    unsigned  EOS_HEALTH : 4; /* 31:28 */
} _bps_bps_0_qos_eos_status_0;

typedef union{
    _bps_bps_0_qos_eos_status_0 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_EOS_STATUS_0;

typedef struct{
    unsigned  EOS_ID : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  STRIPE_ACTIVE_CYC : 28; /* 31:4 */
} _bps_bps_0_qos_eos_status_1;

typedef union{
    _bps_bps_0_qos_eos_status_1 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_EOS_STATUS_1;

typedef struct{
    unsigned  EOS_ID : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  STRIPE_IDLE_CYC : 28; /* 31:4 */
} _bps_bps_0_qos_eos_status_2;

typedef union{
    _bps_bps_0_qos_eos_status_2 bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_EOS_STATUS_2;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _bps_bps_0_qos_spare;

typedef union{
    _bps_bps_0_qos_spare bitfields,bits;
    unsigned int u32All;

} BPS_BPS_0_QOS_SPARE;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/

typedef enum{
    BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_MAXSIZE  = 0x0,
    BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_MAXSIZE_DIV2  = 0x1,
    BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_MAXSIZE_DIV4  = 0x2,
    BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_MAXSIZE_DIV8  = 0x3
} BPS_BPS_0_CDM_BL_FIFO_CFG_REQ_SIZE_ENUM;


typedef enum{
    BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_BITS_0_31  = 0x0,
    BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_BITS_32_63  = 0x1,
    BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_BITS_64_95  = 0x2,
    BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_BITS_96_127  = 0x3
} BPS_BPS_0_CDM_BUS_MISR_CFG_1_MISR_RD_WORD_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_LUT_SEL_RED_LUT  = 0x1,
    BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_LUT_SEL_BLUE_LUT  = 0x2
} BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_PEDESTAL_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_PEDESTAL_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_LUT_SEL_LUT  = 0x1
} BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_LINEARIZATION_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_LINEARIZATION_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_LUT_SEL_PDAF_LUT  = 0x1
} BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_BPC_PDPC_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_BPC_PDPC_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_LUT_SEL_NOISE_LUT  = 0x1
} BPS_BPS_0_CLC_GIC_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_GIC_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_GIC_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_NOISE_LUT0  = 0x1,
    BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_NOISE_LUT1  = 0x2,
    BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_ACTIVITY_LUT  = 0x3,
    BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_DARK_LUT  = 0x4
} BPS_BPS_0_CLC_ABF_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_ABF_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_ABF_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_LUT_SEL_RED_LUT  = 0x1,
    BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_LUT_SEL_BLUE_LUT  = 0x2
} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_LENS_ROLLOFF_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_LENS_ROLLOFF_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_HDR_BHIST_RAM0  = 0x1,
    BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_HDR_BHIST_RAM1  = 0x2,
    BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_HDR_BHIST_RAM2  = 0x3
} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_STATS_HDR_BHIST_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_STATS_HDR_BHIST_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_LUT_SEL_GTM_LUT0  = 0x1
} BPS_BPS_0_CLC_GTM_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_GTM_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_GTM_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_GLUT_CH0_LUT  = 0x1,
    BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_GLUT_CH1_LUT  = 0x2,
    BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_GLUT_CH2_LUT  = 0x3
} BPS_BPS_0_CLC_GLUT_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_GLUT_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_GLUT_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_NO_LUT_SELECTED  = 0x0,
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_LNR_GAIN_ARR  = 0x1,
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_MERGED_FNR_GAIN_ARR_GAIN_CLAMP_ARR  = 0x2,
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_FNR_AC_TH_ARR  = 0x3,
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_SNR_GAIN_ARR  = 0x4,
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_BLEND_LNR_GAIN_ARR  = 0x5,
    BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_BLEND_SNR_GAIN_ARR  = 0x6
} BPS_BPS_0_CLC_HNR_DMI_LUT_CFG_LUT_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_HNR_DMI_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK0  = 0x0,
    BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_BANK_SEL_LUT_BANK1  = 0x1
} BPS_BPS_0_CLC_HNR_MODULE_LUT_BANK_CFG_BANK_SEL_ENUM;


typedef enum{
    BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_FULL_FRAME  = 0x0,
    BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_LEFT_STRIPE  = 0x1,
    BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_RIGHT_STRIPE  = 0x2,
    BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_MIDDLE_STRIPE  = 0x3
} BPS_BPS_0_BUS_RD_CLIENT_0_CCIF_META_DATA_STRIPE_LOCATION_ENUM;


typedef enum{
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_BYPASS  = 0x0,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN8  = 0x1,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_10  = 0x2,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_12  = 0x3,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_14  = 0x4,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN32_20  = 0x5,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ARGB16_10  = 0x6,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ARGB16_12  = 0x7,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ARGB16_14  = 0x8,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN32  = 0x9,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN64  = 0xa,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_TP10  = 0xb,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI8  = 0xc,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI10  = 0xd,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI12  = 0xe,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_MIPI14  = 0xf,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN16_16  = 0x10,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_BYPASS_SWAP  = 0x11,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_PLAIN8_SWAP  = 0x12
} BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_MODE_ENUM;


typedef enum{
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_LSB_ALIGNED  = 0x0,
    BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_MSB_ALIGNED  = 0x1
} BPS_BPS_0_BUS_RD_CLIENT_0_UNPACK_CFG_0_ALIGNMENT_ENUM;


typedef enum{
    BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_0_31  = 0x0,
    BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_32_63  = 0x1,
    BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_64_95  = 0x2,
    BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_BITS_96_127  = 0x3
} BPS_BPS_0_BUS_RD_CLIENT_0_MISR_CFG_1_RD_WORD_SEL_ENUM;

#endif // TITAN170_BPS_H
